370 Instructions  Problem-State

Introduction
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This document is intended to be used as a quick reference for the mainframe, problem-state, non-floating point instructions.

The source code for a sample program that executes each of the problem-state, non-floating point instructions provides additional detail. This information is available via an Internet Connection or Local Access.

Instruction List sequenced by Mnemonic Opcode
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The following list is sequenced by the Mnemonic Opcode.

Instruction List sequenced by Hexadecimal Opcode
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The following list is sequenced by the Hexadecimal Opcode.

Instruction Overview
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This program may serve as a tutorial for programmers that are new to 370 assembler or as a reference for experienced programmers.

A, Add
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The full word (4 bytes) located at the storage address specified by operand-2 (x2+b2+d2} is added to the register specified by operand-1(r1). Operand-2 remains unchanged. The condition code is set as shown below.

AH, Add Halfword
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The half word (2 bytes) located at the storage address specified by operand-2 (x2+b2+d2) is added to the register specified by operand-1 (r1). Operand-2 remains unchanged. The condition code is set as shown below.

AL, Add Logical
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The full word (4 bytes) located at the storage address specified by operand-2 (x2+b2+d2) is added to the register specified by operand-1 (r1). Operand-2 remains unchanged. The condition code is set as shown below.

ALR, Add Logical Registers
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The register specified by operand-2 (r2) is added to the register specified by operand-1 (r1). Operand-2 remains unchanged. The condition code is set as shown below.

AP, Add Packed (Decimal)
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The data string located at the storage address specified by operand-2 (b2+d2) is added to the data string located at the storage address specified by operand-1 (b1+d1). Operand-2 remains unchanged.

The operands may be different lengths with a maximum length of 16 bytes (or 31 digits since this is packed) for each operand. The condition code is set as shown below.

AR, Add Registers
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The register specified by operand-2 (r2) is added to the register specified by operand-1 (r1). Operand-2 remains unchanged. The condition code is set as shown below.

BAL, Branch and Link
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The next sequential address is placed in operand-1 (r1) as linkage information, a branch to operand-2 (x2+b2+d2) is performed.

This instruction was originally intended for use with 24-bit addressing and is still provided for back-level compatibility. Only the rightmost 24 bits (bits 8-31) of the full word are used when branching or linking. The first 8 bits (bits 0-7) are not used as part of the address.

Note:  This instruction will work with 31-bit addressing mode but it is recommended that the BAS instruction be used instead of the BAL instruction.

BALR, Branch and Link Register
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The next sequential address is placed in operand-1 (r1) as linkage information, a branch to operand-2 (r2) is performed.

This instruction was originally intended for use with 24-bit addressing and is still provided for back-level compatibility. Only the rightmost 24 bits (bits 8-31) of the full word are used when branching or linking. The first 8 bits (bits 0-7) are not used as part of the address.

Note:  This instruction will work with 31-bit addressing mode but it is recommended that the BASR instruction be used instead of the BALR instruction.

BAS, Branch and Save
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The next sequential address is placed in operand-1 (r1) as linkage information, a branch to operand-2 (x2+b2+d2) is performed.

This instruction was introduced for use with 31-bit addressing and also works with 24-bit addressing mode. Only the rightmost 31 bits (bits 1-31) of the full word are used when branching or linking. The first bit (bit 0) is not used as part of the address.

BASR, Branch and Save Register
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The next sequential address is placed in operand-1 (r1) as linkage information, a branch to operand-2 (r2) is performed.

This instruction was introduced for use with 31-bit addressing and also works with 24-bit addressing mode. Only the rightmost 31 bits (bits 1-31) of the full word are used when branching or linking. The first bit (bit 0) is not used as part of the address.

BASSM, Branch and Save and Set Mode
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The next sequential address is placed in operand-1 (r1) as linkage information, a branch to operand-2 (r2) is performed. The addressing mode is also set by this instruction.

BC, Branch on Condition
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If the condition-code (cc) has a "bit-ON" match with the instruction-mask (m1) then branch to the address specified by operand-2 (x2+b2+d2) else do the next sequential instruction.

Note:  The following table shows the Condition Code to Instruction-Mask relationship.

BCR, Branch on Condition Register
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If the condition-code (cc) has a "bit-ON" match with the instruction-mask (m1) then branch to the address specified by operand-2 (r2) else do the next sequential instruction.

Note:  The following table shows the Condition Code to Instruction-Mask relationship.

BCT, Branch on Count
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A one is subtracted from operand 1 (r1). If r1 decrements to zero then normal instruction sequencing proceeds else branch to address specified by operand 2.

BCTR, Branch on Count Register
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A one is subtracted from operand 1 (r1). If r1 decrements to zero then normal instruction sequencing proceeds else branch to address specified by operand 2

BSM, Branch and Set Mode
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A branch is performed and the addressing mode is also set by this instruction.

BXH, Branch on Index High
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Operand-1 (r1) is the index value that will be incremented. Operand-2 (b2+d2) is the address to branch to when the compare conditions are met. Operand-3 (r3) may be a single register or a register pair.

If operand-3 register number is even then a register pair are used as the increment and the compare value. If operand-3 is odd a single register is used as both the increment and the compare value. The increment is a signed binary number and may be used to increase or decrease the value in Operand-1

When the BXH instruction is executed the incrementing value specified by operand-3 is added to operand-1. Operand-1 is then compared with the compare value specified by operand-3 and if operand-1 is high then a branch is performed. Otherwise, the next sequential instruction is executed.

BXLE, Branch on Index Low or Equal
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Operand-1 (r1) is the index value that will be incremented. Operand-2 (b2+d2) is the address to branch to when the compare conditions are met. Operand-3 (r3) may be a single register or a register pair.

If operand-3 register number is even then a register pair are used as the increment and the compare value. If operand-3 is odd a single register is used as both the increment and the compare value. The increment is a signed binary number and may be used to increase or decrease the value in Operand-1

When the BXLE instruction is executed the incrementing value specified by operand-3 is added to operand-1. Operand-1 is then compared with the compare value specified by operand-3 and if operand-1 is low or equal then a branch is performed. Otherwise, the next sequential instruction is executed.

C, Compare
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Operand-1 (r1) is compared with the data string located at the storage address specifed by operand-2 (x2+b2+d2) . The result is posted in the condition code.

CDS, Compare Double and Swap
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Operand-1 (r1) and operand-2 (b2+d2) are compared. If equal then operand-3 (r3) is stored at the storage address specified by operand-2 (b2+d2). Otherwise, the data string located at the address specified by operand-2 (b2+d2) is loaded into operand-1 (r1). The operands are 64 bits.

CH, Compare Halfword
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Operand-1 (r1) is compared with the data string located at the storage address specifed by operand-2 (x2+b2+d2) . The result is posted in the condition code.

CL, Compare Logical
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Operand-1 (r1) is compared with the data string located at the storage address specified by operand-2 (x2+b2+d2). The result is posted in the condition code. This is a full word (32-bit) comparison.