370 Instructions
Problem-State
  Table of Contents  v-16.09.01 - asmins01.htm 
  Introduction
  List by Mnemonic Opcode
 
   A   B   C   D   E  I L M
  N O P S T U X Z
  Extended Mnemonics for Branching
  List by Hexadecimal Opcode
  Instruction Overview
  A, Add
  AH, Add Halfword
  AL, Add Logical
  ALR, Add Logical Registers
  AP, Add Packed (Decimal)
  AR, Add Registers
  BAL, Branch and Link
  BALR, Branch and Link Register
  BAS, Branch and Save
  BASR, Branch and Save Register
  BASSM, Branch and Save, Set Mode
  BC, Branch on Condition
  BCR, Branch on Condition Register
  BCT, Branch on Count
  BCTR, Branch on Count Register
  BSM, Branch and Set Mode
  BXH, Branch on Index High
  BXLE, Branch on Index Low or Equal
  C, Compare
  CDS, Compare Double and Swap
  CH, Compare Halfword
  CL, Compare Logical
  CLC, Compare Logical Characters
  CLCL, Compare Logical Characters Long
  CLI, Compare Logical Immediate
  CLM, Compare Logical under Mask
  CLR, Compare Logical Registers
  CP, Compare Packed (Decimal)
  CR, Compare Registers
  CS, Compare and Swap
  CVB, Convert to Binary
  CVD, Convert to Decimal
  D, Divide
  DP, Divide Packed (Decimal)
  DR, Divide Registers
  ED, Edit
  EDMK, Edit and Mark
  EX, Execute
  IC, Insert Characters
  ICM, Insert Character under Mask
  L, Load
  LA, Load Address
  LCR, Load Complement Registers
  LH, Load Halfword
  LM, Load Multiples
  LNR, Load Negative Registers
  LPR, Load Positive Registers
  LR, Load Register
  LTR, Load and Test Register
  M, Multiply
  MH, Multiply Halfword
  MP, Multiply Packed (Decimal)
  MR, Multiply Registers
  MVC, Move Characters
  MVCIN, Move Characters Inverse
  MVCL, Move Characters Long
  MVI, Move Immediate
  MVN, Move Numerics
  MVO, Move with Offset
  MVZ, Move Zones
  N, And
  NC, And Characters
  NI, And Immediate
  NR, And Registers
  O, Or
  OC, Or Characters
  OI, Or Immediate
  OR, Or Registers
  PACK, Pack
  S, Subtract
  SH, Subtract Halfword
  SL, Subtract Logical
  SLA, Shift Left Single
  SLDA, Shift Left Double
  SLDL, Shift Left Double Logical
  SLL, Shift Left Single Logical
  SLR, Subtract Logical Registers
  SP, Subtract Packed (Decimal)
  SR, Subtract Registers
  SRA, Shift Right Single
  SRDA, Shift Right Double
  SRDL, Shift Right Double Logical
  SRL, Shift Right Single Logical
  SRP, Shift and Round Decimal
  ST, Store
  STC, Store Character
  STCM, Store Characters under Mask
  STH, Store Halfword
  STM, Store Multiples
  SVC, Supervisor Call
  TM, Test under Mask
  TR, Translate
  TRT, Translate and Test
  UNPK, Unpack
  X, Exclusive Or
  XC, Exclusive Or Characters
  XI, Exclusive Or Immediate
  XR, Exclusive Or Registers
  ZAP, Zero and Add Packed
  Summary
  Software Agreement and Disclaimer
  Downloads and Links
  Current Server or Internet Access
  Internet Access Required
  Glossary of Terms
  Comments or Feedback
  Company Overview
The SimoTime Home Page 

Table of Contents Previous Section Next Section Introduction

This document is intended to be used as a quick reference for the mainframe, problem-state, non-floating point instructions.

The source code for a sample program that executes each of the problem-state, non-floating point instructions provides additional detail. This information is available via an Internet Connection or Local Access. NORMAL


We have made a significant effort to ensure the documents and software technologies are correct and accurate. We reserve the right to make changes without notice at any time. The function delivered in this version is based upon the enhancement requests from a specific group of users. The intent is to provide changes as the need arises and in a timeframe that is dependent upon the availability of resources.

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All Rights Reserved

Table of Contents Previous Section Next Section List by Mnemonic Opcode

The following is an instruction list that is sequenced by the Mnemonic Opcode. The 1st colum (Instruction) is the full name. The 2nd column (Mnemonic) is the Mnemonic Operation Code (or OpCode) that would be used in an HLASM Program. The 3rd column (Hex) is the one-bye OpCode that is generated and used at execution time. The 4th column (Format) is the format of the instruction as it would be written within an HLASM program.

  Instruction Mnemonic  Hex  Format
  Add A 5A R1,D2(X2,B2)
  Add Halfword AH 4A R1,D2(X2,B2)
  Add Logical AL 5E R1,D2(X2,B2)
  Add Logical Registers ALR 1E R1,R2
  Add Packed (Decimal) AP FA D1(L1,B1),D2(L2,B2)
  Add Registers AR 1A R1,R2
  Branch and Link BAL 45 R1,D2(X2,B2)
  Branch and Link Register BALR 05 R1,R2
  Branch and Save BAS 4D R1,D2(X2,B2)
  Branch and Save Register BASR 0D R1,R2
  Branch, Save and Set Mode BASSM 0C R1,R2
  Branch on Condition BC 47 M1,D2(X2,B2)
  Branch on Condition Register BCR 07 M1,R2
  Branch on Count BCT 46 R1,D2((X2,B2)
  Branch on Count Register BCTR 06 R1,R2
  Branch and Set Mode BSM 0B R1,R2
  Branch on Index High BXH 86 R1,R3,D2(B2)
  Branch on Index Low/Equal BXLE 87 R1,R3,D2(B2)
  Compare C 59 R1,D2(X2,B2)
  Compare Double and Swap CDS BB R1,R3,D2(B2)
  Compare Halfword CH 49 R1,D2(X2,B2)
  Compare Logical CL 55 R1,D2(X2,B2)
  Compare Logical Characters CLC D5 D1(L,B1),D2(B2)
  Compare Logical Characters Long  CLCL 0F R1,R2
  Compare Logical Immediate CLI 95 D1(B1),I2
  Compare Logical under Mask CLM BD R1,M3,D2(B2)
  Compare Logical Registers CLR 15 R1,R2
  Compare Packed (Decimal) CP F9 D1(L1,B1),D2(L2,B2)
  Compare Registers CR 19 R1,R2
  Compare and Swap CS BA R1,R3,D2(B2)
  Convert to Binary CVB 4F R1,D2((X2,B2)
  Convert to Decimal CVD 4E R1,D2((X2,B2)
  Divide D 5D R1,D2((X2,B2)
  Divide Packed (Decimal) DP FD D1(L1,B1),D2(L2,B2)
  Divide Registers DR 1D R1,R2
  Edit ED DE D1(L1,B1),D2(B2)
  Edit and Mark EDMK DF D1(L1,B1),D2(B2)
  Execute EX 44 R1,D2(X2,B2)
  Insert Character IC 43 R1,D2(X2,B2)
  Insert Character under Mask ICM BF R1,M3,D2(B2)
  Load L 58 R1,D2(X2,B2)
  Load Address LA 41 R1,D2(X2,B2)
  Load Complement Registers LCR 13 R1,R2
  Load Halfword LH 48 R1,D2(X2,B2)
  Load Multiple LM 98 R1,R3,D2(B2)
  Load Negative LNR 11 R1,R2
  Load Postive LPR 10 R1,R2
  Load Register LR 18 R1,R2
  Load and Test Register LTR 12 R1,R2
  Multiply M 5C R1,D2(X2,B2)
  Multiply Halfword MH 4C R1,D2(X2,B2)
  Multiply Packed (Decimal) MP FC D1(L1,B1),D2(L2,B2)
  Multiply Registers MR 1C R1,R2
  Move Characters MVC D2 D1(L,B1),D2(B2)
  Move Inverse MVCIN E8 D1(L,B1),D2(B2)
  Move Characters Long MVCL 0E R1,R2
  Move Immediate MVI 92 D1(B1),I2
  Move Numerics MVN D1 D1(L,B1),D2(B2)
  Move with Offset MVO F1 D1(L1,B1),D2(L2,B2)
  Move Zones MVZ D3 D1(L,B1),D2(B2)
  aNd N 54 R1,D2(X2,B2)
  aNd Characters NC D4 D1(L,B1),D2(B2)
  aNd Immediate NI 94 D1(B1),I2
  aNd Registers NR 14 R1,R2
  Or O 56 R1,D2(X2,B2)
  Or Characters OC D6 D1(L,B1),D2(B2)
  Or Immediate OI 96 D1(B1),I2
  Or Registers OR 16 R1,R2
  Pack PACK F2 D1(L1,B1),D2(L2,B2)
  Subtract S 5B R1,D2(X2,B2)
  Subtract Halfword SH 4B R1,D2(X2,B2)
  Subtract Logical SL 5F R1,D2(X2,B2)
  Shift Left Single SLA 8B R1,D2(B2)
  Shift Left Double SLDA 8F R1,D2(B2)
  Shift Left Double Logical SLDL 8D R1,D2(B2)
  Shift Left Single Logical SLL 89 R1,D2(B2)
  Subtract Logical Registers SLR 1F R1,R2
  Subtract Packed (Decimal) SP FB D1(L1,B1),D2(L2,B2)
  Subtract Registers SR 1B R1,R2
  Shift Right Single SRA 8A R1,D2(B2)
  Shift Right Double SRDA 8E R1,D2(B2)
  Shift Right Double Logical SRDL 8C R1,D2(B2)
  Shift Right Single Logical SRL 88 R1,D2(B2)
  Shift and Round Decimal SRP F0 D1(L1,B1),D2(B2),I3 
  Store ST 50 R1,D2(X2,B2)
  Store Character STC 42 R1,D2(X2,B2)
  Store Character under Mask STCM BE R1,M3,D2(B2)
  Store Halfword STH 40 R1,D2(X2,B2)
  Store Multiple STM 90 R1,R3,D2(B2)
  Supervisor Call SVC 0A I1
  Test under Mask TM 91 D1(B1),I2
  Translate TR DC D1(L1,B1),D2(B2)
  Translate and Test TRT DD D1(L1,B1),D2(B2)
  Unpack UNPK F3 D1(L1,B1),D2(L2,B2)
  eXclusive Or X 57 R1,D2(X2,B2)
  eXclusive Or Characters XC D7 D1(L,B1),D2(B2)
  eXclusive Or Immediate XI 97 D1(B1),I2
  eXclusive Or Registers XR 17 R1,R2
  Zero Add Packed ZAP F8 D1(L1,B1),D2(L2,B2)

Table of Contents Previous Section Next Section List by Hexadecimal Opcode

The following is an instruction list that is sequenced by the Hexadecimal Opcode. The 1st colum (Instruction) is the full name. The 2nd column (Mnemonic) is the Mnemonic Operation Code (or OpCode) that would be used in an HLASM Program. The 3rd column (Hex) is the one-bye OpCode that is generated and used at execution time. The 4th column (Format) is the format of the instruction as it would be written within an HLASM program.

  Instruction Mnemonic  Hex  Format
  Branch and Link Register BALR 05 R1,R2
  Branch on Count Register BCTR 06 R1,R2
  Branch on Condition Register BCR 07 M1,R2
  Supervisor Call SVC 0A I1
  Branch and Set Mode BSM 0B R1,R2
  Branch, Save and Set Mode BASSM 0C R1,R2
  Branch and Save Register BASR 0D R1,R2
  Move Characters Long MVCL 0E R1,R2
  Compare Logical Characters Long  CLCL 0F R1,R2
  Load Postive LPR 10 R1,R2
  Load Negative LNR 11 R1,R2
  Load and Test Register LTR 12 R1,R2
  Load Complement Registers LCR 13 R1,R2
  aNd Registers NR 14 R1,R2
  Compare Logical Registers CLR 15 R1,R2
  Or Registers OR 16 R1,R2
  eXclusive Or Registers XR 17 R1,R2
  Load Register LR 18 R1,R2
  Compare Registers CR 19 R1,R2
  Add Registers AR 1A R1,R2
  Subtract Registers SR 1B R1,R2
  Multiply Registers MR 1C R1,R2
  Divide Registers DR
1D R1,R2
  Add Logical Registers ALR 1E R1,R2
  Subtract Logical Registers SLR 1F R1,R2
  Store Halfword STH 40 R1,D2(X2,B2)
  Load Address LA 41 R1,D2(X2,B2)
  Store Character STC 42 R1,D2(X2,B2)
  Insert Character IC 43 R1,D2(X2,B2)
  Execute EX 44 R1,D2(X2,B2)
  Branch and Link BAL 45 R1,D2(X2,B2)
  Branch on Count BCT 46 R1,D2((X2,B2)
  Branch on Condition BC 47 M1,D2(X2,B2)
  Load Halfword LH 48 R1,D2(X2,B2)
  Compare Halfword CH 49 R1,D2(X2,B2)
  Add Halfword AH 4A R1,D2(X2,B2)
  Subtract Halfword SH 4B R1,D2(X2,B2)
  Multiply Halfword MH 4C R1,D2(X2,B2)
  Branch and Save BAS 4D R1,D2(X2,B2)
  Convert to Decimal CVD 4E R1,D2((X2,B2)
  Convert to Binary CVB 4F R1,D2((X2,B2)
  Store ST 50 R1,D2(X2,B2)
  aNd N 54 R1,D2(X2,B2)
  Compare Logical CL 55 R1,D2(X2,B2)
  Or O 56 R1,D2(X2,B2)
  eXclusive Or X 57 R1,D2(X2,B2)
  Load L 58 R1,D2(X2,B2)
  Compare C 59 R1,D2(X2,B2)
  Add A 5A R1,D2(X2,B2)
  Subtract S 5B R1,D2(X2,B2)
  Multiply M 5C R1,D2(X2,B2)
  Divide D 5D R1,D2((X2,B2)
  Add Logical AL 5E R1,D2(X2,B2)
  Subtract Logical SL 5F R1,D2(X2,B2)
  Branch on Index High BXH 86 R1,R3,D2(B2)
  Branch on Index Low/Equal BXLE 87 R1,R3,D2(B2)
  Shift Right Single Logical SRL 88 R1,D2(B2)
  Shift Left Single Logical SLL 89 R1,D2(B2)
  Shift Right Single SRA 8A R1,D2(B2)
  Shift Left Single SLA 8B R1,D2(B2)
  Shift Right Double Logical SRDL 8C R1,D2(B2)
  Shift Left Double Logical SLDL 8D R1,D2(B2)
  Shift Right Double SRDA 8E R1,D2(B2)
  Shift Left Double SLDA 8F R1,D2(B2)
  Store Multiple STM 90 R1,R3,D2(B2)
  Test under Mask TM 91 D1(B1),I2
  Move Immediate MVI 92 D1(B1),I2
  aNd Immediate NI 94 D1(B1),I2
  Compare Logical Immediate CLI 95 D1(B1),I2
  Or Immediate OI 96 D1(B1),I2
  eXclusive Or Immediate XI 97 D1(B1),I2
  Load Multiple LM 98 R1,R3,D2(B2)
  Compare and Swap CS BA R1,R3,D2(B2)
  Compare Double and Swap CDS BB R1,R3,D2(B2)
  Compare Logical under Mask CLM BD R1,M3,D2(B2)
  Store Character under Mask STCM BE R1,M3,D2(B2)
  Insert Character under Mask ICM BF R1,M3,D2(B2)
  Move Numerics MVN D1 D1(L,B1),D2(B2)
  Move Characters MVC D2 D1(L,B1),D2(B2)
  Move Zones MVZ D3 D1(L,B1),D2(B2)
  aNd Characters NC D4 D1(L,B1),D2(B2)
  Compare Logical Characters CLC D5 D1(L,B1),D2(B2)
  Or Characters OC D6 D1(L,B1),D2(B2)
  eXclusive Or Characters XC D7 D1(L,B1),D2(B2)
  Translate TR DC D1(L1,B1),D2(B2)
  Translate and Test TRT DD D1(L1,B1),D2(B2)
  Edit ED DE D1(L1,B1),D2(B2)
  Edit and Mark EDMK DF D1(L1,B1),D2(B2)
  Move Inverse MVCIN E8 D1(L,B1),D2(B2)
  Shift and Round Decimal SRP F0 D1(L1,B1),D2(B2),I3 
  Move with Offset MVO F1 D1(L1,B1),D2(L2,B2)
  Pack PACK F2 D1(L1,B1),D2(L2,B2)
  Unpack UNPK F3 D1(L1,B1),D2(L2,B2)
  Zero Add Packed ZAP F8 D1(L1,B1),D2(L2,B2)
  Compare Packed (Decimal) CP F9 D1(L1,B1),D2(L2,B2)
  Add Packed (Decimal) AP FA D1(L1,B1),D2(L2,B2)
  Subtract Packed (Decimal) SP FB D1(L1,B1),D2(L2,B2)
  Multiply Packed (Decimal) MP FC D1(L1,B1),D2(L2,B)
  Divide Packed (Decimal) DP FD D1(L1,B1),D2(L2,B2)

Table of Contents Previous Section Next Section Instruction Overview

This program may serve as a tutorial for programmers that are new to 370 assembler or as a reference for experienced programmers.

Table of Contents Previous Section Next Section A, Add

The full word (4 bytes) located at the storage address specified by operand-2 (X2+B2+D2} is added to the register specified by operand-1(R1). Operand-2 remains unchanged. The condition code is set as shown below.

           
   
   
 
 
X2=index-register
   
   
   
   
B2=base register
D2=displacement
   
5A
RX
BDDD
A R1,D2(X2,B2)
R1=register
 
 
   
   
Condition Code
0 - op1 = 0, n/o
1 - op1 < 0, n/o
2 - op1 > 0, n/o
3 - overflow
 
A, Add Instruction, the operand format is R1,D2(X2,B2)

 

Table of Contents Previous Section Next Section AH, Add Halfword

The half word (2 bytes) located at the storage address specified by operand-2 (x2+b2+d2) is added to the register specified by operand-1 (r1). Operand-2 remains unchanged. The condition code is set as shown below.

           
   
   
 
 
X2=index
   
   
   
   
B2=base register
D2=displacement
   
4A
RX
BDDD
AH R1,D2(X2,B2)
R1=register
 
 
   
   
Condition Code
0 - op1 = 0, n/o
1 - op1 < 0, n/o
2 - op1 > 0, n/o
3 - overflow
 
AH, Add Halfword Instruction, the operand format is R1,D2(X2,B2)

 

Table of Contents Previous Section Next Section AL, Add Logical

The full word (4 bytes) located at the storage address specified by operand-2 (x2+b2+d2) is added to the register specified by operand-1 (r1). Operand-2 remains unchanged. The condition code is set as shown below.

           
   
   
 
 
X2=index
   
   
   
   
B2=base register
D2=displacement
   
5E
RX
BDDD
AL R1,D2(X2,B2)
R1=register
 
 
   
   
Condition Code
0 - zero, no-carry
1 - not-zero, no-carry
2 - zero, carry
3 - not-zero, carry
 
AL, Add Logical Instruction, the operand format is R1,D2(X2,B2)

 

Table of Contents Previous Section Next Section ALR, Add Logical Registers

The register specified by operand-2 (r2) is added to the register specified by operand-1 (r1). Operand-2 remains unchanged. The condition code is set as shown below.

         
   
   
R2=register
1E
RR
ALR R1,R2
R1=register
 
 
   
   
Condition Code
0 - zero, no-carry
1 - not-zero, no-carry
2 - zero, carry
3 - not-zero, carry
 
ALR, Add Logical Registers Instruction, the operand format is R1,R2

 

Table of Contents Previous Section Next Section AP, Add Packed (Decimal)

The data string located at the storage address specified by operand-2 (b2+d2) is added to the data string located at the storage address specified by operand-1 (b1+d1). Operand-2 remains unchanged.

The operands may be different lengths with a maximum length of 16 bytes (or 31 digits since this is packed) for each operand. The condition code is set as shown below.

               
   
   
 
 
 
 
L2=length
   
   
   
   
B2=base register
D2=displacement
   
FA
LL
BDDD
BDDD
AP D1(L1,B1),D2(L2,B2)
   
L1=length
 
 
   
   
   
   
B1=base register
D1=displacement
 
 
 
 
   
   
Condition Code
0 - op1 = 0, n/o
1 - op1 < 0, n/o
2 - op1 > 0, n/o
3 - overflow
 
AP, Add Packed (Decimal) Instruction, the operand format is D1(L1,B1),D2(L2,B2)

 

Table of Contents Previous Section Next Section AR, Add Registers

The register specified by operand-2 (R2) is added to the register specified by operand-1 (R1). Operand-2 remains unchanged. The condition code is set as shown below.

         
   
   
R2=register
1A
RR
AR R1,R2
R1=register
 
 
   
   
Condition Code
0 - op1 = 0, n/o
1 - op1 < 0, n/o
2 - op1 > 0, n/o
3 - overflow
 
AR, Add Registers Instruction, the operand format is R1,R2

 

Table of Contents Previous Section Next Section BAL, Branch and Link

The next sequential address is placed in operand-1 (r1) as linkage information, a branch to operand-2 (x2+b2+d2) is performed.

             
   
   
 
 
X2=index
   
   
   
   
B2=base register
D2=displacement
   
45
RX
BDDD
BAL R1,D2(X2,B2)
R1=register
 
 
   
   
Condition Code
The code remains unchanged.
 
BAL, Branch and Link Instruction, the format is R1,D2(X2,B2)

This instruction was originally intended for use with 24-bit addressing and is still provided for back-level compatibility. Only the rightmost 24 bits (bits 8-31) of the full word are used when branching or linking. The first 8 bits (bits 0-7) are not used as part of the address.

Note:  This instruction will work with 31-bit addressing mode but it is recommended that the BAS instruction be used instead of the BAL instruction.

Table of Contents Previous Section Next Section BALR, Branch and Link Register

The next sequential address is placed in operand-1 (r1) as linkage information, a branch to operand-2 (r2) is performed.

         
   
   
R2=register
05
RR
BALR R1,R2
R1=register
 
 
   
   
Condition Code
The code remains unchanged.
 
Note: When the operand 2 value is zero, the link information is loaded without branching.
BALR, Branch and Link Register Instruction, the operand format is R1,R2

This instruction was originally intended for use with 24-bit addressing and is still provided for back-level compatibility. Only the rightmost 24 bits (bits 8-31) of the full word are used when branching or linking. The first 8 bits (bits 0-7) are not used as part of the address.

Note:  This instruction will work with 31-bit addressing mode but it is recommended that the BASR instruction be used instead of the BALR instruction.

Table of Contents Previous Section Next Section BAS, Branch and Save

The next sequential address is placed in operand-1 (r1) as linkage information, a branch to operand-2 (x2+b2+d2) is performed.

             
   
   
 
 
X2=index
   
   
   
   
B2=base register
D2=displacement
   
4D
RX
BDDD
BAS R1,D2(X2,B2)
R1=register
 
 
   
   
Condition Code
The code remains unchanged
 
BAS, Branch and Save Instruction, the format is R1,D2(X2,B2)

This instruction was introduced for use with 31-bit addressing and also works with 24-bit addressing mode. Only the rightmost 31 bits (bits 1-31) of the full word are used when branching or linking. The first bit (bit 0) is not used as part of the address.

Table of Contents Previous Section Next Section BASR, Branch and Save Register

The next sequential address is placed in operand-1 (R1) as linkage information, a branch to operand-2 (R2) is performed.

         
   
   
R2=register
0D
RR
BASR   R1,R2
R1=register
 
 
   
   
Condition Code
The code remains unchanged
 
Note: When the operand 2 value is zero, the link information is loaded into R1 without branching.
BASR, Branch and Save Register Instruction, the operand format is R1,R2

This instruction was introduced for use with 31-bit addressing and also works with 24-bit addressing mode. Only the rightmost 31 bits (bits 1-31) of the full word are used when branching or linking. The first bit (bit 0) is not used as part of the address.

Table of Contents Previous Section Next Section BASSM, Branch and Save, Set Mode

The next sequential address is placed in operand-1 (r1) as linkage information, a branch to operand-2 (r2) is performed. The addressing mode is also set by this instruction.

         
   
   
R2=register
0C
RR
BASSM R1,R2
R1=register
 
 
   
   
 
BASSM, Branch and Save and Set Mode Instruction, the operand format is R1,R2

 

Table of Contents Previous Section Next Section BC, Branch on Condition

If the condition-code (cc) has a "bit-ON" match with the instruction-mask (m1) then branch to the address specified by operand-2 (x2+b2+d2) else do the next sequential instruction.

           
   
   
 
 
X2=index
   
   
   
   
B2=base register
D2=displacement
   
47
MX
BDDD
BC M1,D2(X2,B2)
M1=mask
 
 
   
   
 
BC, Branch on Condition Instruction, the operand format is M1,D2(X2,B2)

Note:  The following table shows the Condition Code to Instruction-Mask relationship.

 cc relationship  mask-bits  hex-code 
 0equal-zero1000x'8x'
 1low-minus0100x'4x'
 2high-plus0010x'2x'
 3overflow0001x'1x'

Table of Contents Previous Section Next Section BCR, Branch on Condition Register

If the condition-code (cc) has a "bit-ON" match with the instruction-mask (m1) then branch to the address specified by operand-2 (r2) else do the next sequential instruction.

         
   
   
R2=register
07
MR
BCR M1,R2
M1=mask
 
 
   
   
 
BCR, Branch on Condition Register Instruction, the operand format is M1,R2

Note:  The following table shows the Condition Code to Instruction-Mask relationship.

 cc relationship  mask-bits  hex-code 
 0equal-zero1000x'8x'
 1low-minus0100x'4x'
 2high-plus0010x'2x'
 3overflow0001x'1x'

Table of Contents Previous Section Next Section BCT, Branch on Count

A one is subtracted from operand 1 (r1). If r1 decrements to zero then normal instruction sequencing proceeds else branch to address specified by operand 2.

           
   
   
 
 
X2=index
   
   
   
   
B2=base register
D2=displacement
   
46
RX
BDDD
BCT R1,D2(X2,B2)
R1=register
 
 
   
   
 
BCT, Branch on Count Instruction, the operand format is R1,D2(X2,B2)

 

Table of Contents Previous Section Next Section BCTR, Branch on Count Register

A one is subtracted from operand 1 (r1). If r1 decrements to zero then normal instruction sequencing proceeds else branch to address specified by operand 2

         
   
   
R2=register
06
RR
BCTR R1,R2
R1=register
 
 
   
   
Condition Code
The code remains unchanged.
 
Note: If r2 is zero then r1 is decremented but a branch is never taken.
BCTR, Branch on Condition Register Instruction, the operand format is R1,R2

 

Table of Contents Previous Section Next Section BSM, Branch and Set Mode

A branch is performed and the addressing mode is also set by this instruction.

         
   
   
R2=register
0B
RR
BSM R1,R2
R1=register
 
 
   
   
 
BSM, Branch and Set Mode Instruction, the operand format is R1,R2

 

Table of Contents Previous Section Next Section BXH, Branch on Index High

Operand-1 (r1) is the index value that will be incremented. Operand-2 (b2+d2) is the address to branch to when the compare conditions are met. Operand-3 (r3) may be a single register or a register pair.

If operand-3 register number is even then a register pair are used as the increment and the compare value. If operand-3 is odd a single register is used as both the increment and the compare value. The increment is a signed binary number and may be used to increase or decrease the value in Operand-1

When the BXH instruction is executed the incrementing value specified by operand-3 is added to operand-1. Operand-1 is then compared with the compare value specified by operand-3 and if operand-1 is high then a branch is performed. Otherwise, the next sequential instruction is executed.

           
R1=register
 
 
   
   
   
   
   
B2=base register
D2=displacement
   
86
RR
BDDD
BXH R1,R3,D2(B2)
R3=register
 
 
   
   
 
BXH, Branch on Index High Instruction, the operand format is R1,R3,D2(B2)

 

Table of Contents Previous Section Next Section BXLE, Branch on Index Low or Equal

Operand-1 (r1) is the index value that will be incremented. Operand-2 (b2+d2) is the address to branch to when the compare conditions are met. Operand-3 (r3) may be a single register or a register pair.

If operand-3 register number is even then a register pair are used as the increment and the compare value. If operand-3 is odd a single register is used as both the increment and the compare value. The increment is a signed binary number and may be used to increase or decrease the value in Operand-1

When the BXLE instruction is executed the incrementing value specified by operand-3 is added to operand-1. Operand-1 is then compared with the compare value specified by operand-3 and if operand-1 is low or equal then a branch is performed. Otherwise, the next sequential instruction is executed.

           
R1=register
 
 
   
   
   
   
   
B2=base register
D2=displacement
   
87
RR
BDDD
BXLE R1,R3,D2(B2)
R3=register
 
 
   
   
 
BXLE, Branch on Index Low or Equal Instruction, the operand format is R1,R3,D2(B2)

 

Table of Contents Previous Section Next Section C, Compare

Operand-1 (r1) is compared with the data string located at the storage address specifed by operand-2 (x2+b2+d2) . The result is posted in the condition code.

           
   
   
 
 
X2=index
   
   
   
   
B2=base register
D2=displacement
   
59
RX
BDDD
C R1,D2(X2,B2)
R1=register
 
 
   
   
Condition Code
0 -equal
1 - op1 is low
2 - op1 is high
3 -  
 
C, Compare Instruction, the operand format is R1,D2(X2,B2)

 

Table of Contents Previous Section Next Section CDS, Compare Double and Swap

Operand-1 (r1) and operand-2 (b2+d2) are compared. If equal then operand-3 (r3) is stored at the storage address specified by operand-2 (b2+d2). Otherwise, the data string located at the address specified by operand-2 (b2+d2) is loaded into operand-1 (r1). The operands are 64 bits.

           
R1=register-pair
 
 
   
   
   
   
   
B2=base register
D2=displacement
   
BB
RR
BDDD
CDS R1,R3,D2(B2)
R3=register-pair
 
 
   
   
 
CDS, Compare Double and Swap Instruction, the operand format is R1,R3,D2(B2)

 

Table of Contents Previous Section Next Section CH, Compare Halfword

Operand-1 (r1) is compared with the data string located at the storage address specifed by operand-2 (x2+b2+d2) . The result is posted in the condition code.

           
   
   
 
 
X2=index
   
   
   
   
B2=base register
D2=displacement
   
49
RX
BDDD
CH R1,D2(X2,B2)
R1=register
 
 
   
   
Condition Code
0 -equal
1 - op1 is low
2 - op1 is high
3 -  
 
CH, Compare Halfword Instruction, the operand format is R1,D2(X2,B2)

 

Table of Contents Previous Section Next Section CL, Compare Logical

Operand-1 (r1) is compared with the data string located at the storage address specified by operand-2 (x2+b2+d2). The result is posted in the condition code. This is a full word (32-bit) comparison.

           
   
   
 
 
X2=index
   
   
   
   
B2=base register
D2=displacement
   
55
RX
BDDD
CL R1,D2(X2,B2)
R1=register
 
 
   
   
Condition Code
0 -equal
1 - op1 is low
2 - op1 is high
3 -  
 
CL, Compare Logical Instruction, the operand format is R1,D2(X2,B2)

 

Table of Contents Previous Section Next Section CLC, Compare Logical Characters

The data string located at the storage address specified by operand-2 (b2+d2) is compared to the data string located at the storage address specified by operand-1 (b1+d1). Both operands remains unchanged.

The number of bytes compared is determined by the length specified in the 2nd byte of the CLC instruction. The length specified is actually the length-1 or x'00' through x'FF'.

The length of each operand is the same. For example, if x'FF' is specified as the length then operand-1 would be 256 bytes and operand-2 would be 256 bytes. The condition code is set as shown below.

               
LL=length
from x'00' to x'FF'
 
 
   
   
   
   
B2=base register
D2=displacement
   
D5
LL
BDDD
BDDD
CLC D1(L,B1),D2(B2)
   
B1=base register
D1=displacement
 
 
 
 
   
   
Condition Code
0 - equal
1 - op1 is low
2 - op1 is high
3 - --
 
CLC, Compare Logical Characters Instruction, the operand format is D1(L,B1),D2(B2)

 

Table of Contents Previous Section Next Section CLCL, Compare Logical Characters Long

The data string identified by operand-1 (R1) is compared with the data string identified by operand-2 (R2). Both operands are register-pairs.

The first register of each operand needs to be loaded with the storage addresses of the data strings to be compared. The second register of each operand needs to be loaded with the length of each operand.

The data strings may be different length. The high-order byte of the second register of operand-2 is treated as the padding character if the operands are different lengths.

The compare proceeds from left to right, low storage to high storage and as each character is found to be equal the length registers are decremented. If the CLCL results in and equal condition then the length registers should be zero with one exception.

Remember, if a pad character was specified in the high-order (bits 0-7) byte of the second register of operand-2 then only the remaining three bytes (bits 8-31) will be zero. The results are posted in the condition code.

           
   
   
R2=register-pair
0F
RR
CLCL R1,R2
R1=register-pair
 
 
   
   
Condition Code
0 - equal
1 - op1 is low
2 - op1 is high
3 -  
 
CLCL, Compare Logical Characters Long Instruction, the operand format is R1,R2

 

Table of Contents Previous Section Next Section CLI, Compare Logical Immediate

Operand-2 (the immediate data that is the second byte of the instruction itself) is compared to the one-byte at the storage address specifed by operand-1 (b1+d1). The results of the compare are posted in the condition code.

           
   
   
B1=base register
D1=displacement
   
95
II
BDDD
CLI D1(B1),I2
I2=immediate
 
 
   
   
Condition Code
0 -equal
1 - op1 is low
2 - op1 is high
3 -  
 
CLI, Compare Logical Immediate Instruction, the operand format is D1(B1),I2

 

Table of Contents Previous Section Next Section CLM, Compare Logical under Mask

Operand-1 (r1) under control of the mask (m3) is compared to the data string located at the storage location specified by operand-2. The results are posted in the condition code.

           
R1=register
 
 
   
   
   
   
   
B2=base register
D2=displacement
   
BD
RM
BDDD
CLM R1,M3,D2(B2)
M1=mask
 
 
   
   
Condition Code
0 -equal or mask-bits all zero
1 - op1 is low
2 - op1 is high
3 -  
 
CLM, Compare Logical under Mask Instruction, the operand format is R1,M3,D2(B2)

 

Table of Contents Previous Section Next Section CLR, Compare Logical Registers

Operand-1 (r1) is compared with operand-2 (r2). The compare is a logical compare of all 32-bits. The results are posted in the condition code.

           
   
   
R2=register
15
RR
CLR R1,R2
R1=register
 
 
   
   
Condition Code
0 - equal
1 - op1 is low
2 - op1 is high
3 -  
 
CLR, Compare Logical Registers Instruction, the operand format is R1,R2

 

Table of Contents Previous Section Next Section CP, Compare Packed (Decimal)

The data string located at the storage address specified by operand-2 (b2+d2) is compared to the data string located at the storage address specified by operand-1 (b1+d1).

The operands may be different lengths with a maximum length of 16 bytes (or 31 digits since this is packed) for each operand. This is an arithmetic comparison. The condition code is set as shown below.

               
   
   
 
 
 
 
L2=length
   
   
   
   
B2=base register
D2=displacement
   
F9
LL
BDDD
BDDD
CP D1(L1,B1),D2(L2,B2)
   
L1=length
 
 
   
   
   
   
B1=base register
D1=displacement
 
 
 
 
   
   
Condition Code
0 - op1 = 0, n/o
1 - op1 < 0, n/o
2 - op1 > 0, n/o
3 - overflow
 
CP, Compare Packed (Decimal) Instruction, the operand format is D1(L1,B1),D2(L2,B2)

 

Table of Contents Previous Section Next Section CR, Compare Registers

The register specified by operand-2 (r2) is compared to the the register specified by operand-1 (r1). Operand-2 remains unchanged. The condition code is set as shown below.

           
   
   
R2=register
19
RR
R1=register
 
 
   
   
Condition Code
0 - equal
1 - op1 is low
2 - op1 is high
3 -  
 
CR, Compare Registers Instruction, the operand format is R1,R2

 

Table of Contents Previous Section Next Section CS, Compare and Swap

Operand-1 (r1) and operand-2 (b2+d2) are compared. If equal then operand-3 (r3) is stored at the storage address specified by operand-2 (b2+d2).

Otherwise, the data string located at the address specified by operand-2 (b2+d2) is loaded into operand-1 (r1). The operands are 32 bits.

           
R1=register
 
 
   
   
   
   
   
B2=base register
D2=displacement
   
BA
RR
BDDD
CS R1,R3,D2(B2)
R3=register
 
 
   
   
 
CS, Compare and Swap Instruction, the operand format is R1,R3,D2(B2)

 

Table of Contents Previous Section Next Section CVB, Convert to Binary

The data string at the storage location specified by operand-2 (X2+B2+D2) is translated from decimal to binary and the result is stored in operand-1 (R1).

Operand-2 remains unchanged and should be an 8-byte packed (15 digit and sign), decimal value.

           
   
   
 
 
X2=index-register
   
   
   
   
B2=base register
D2=displacement
   
4F
RX
BDDD
CVB R1,D2(X2,B2)
R1=register
 
 
   
   
 
CVB, Convert to Binary Instruction, the operand format is R1,D2(X2,B2)

 

Table of Contents Previous Section Next Section CVD, Convert to Decimal

Operand-1 (R1) is translated from binary to decimal and the result is stored at the storage location specified by operand-2 (X2+B2+D2). Operand-1 remains unchanged.

Operand-2 should be an 8-byte packed (15 digit and sign), decimal value.

           
   
   
 
 
X2=index-register
   
   
   
   
B2=base register
D2=displacement
   
4E
RX
BDDD
CVD R1,D2(X2,B2)
R1=register
 
 
   
   
 
CVD, Convert to Decimal Instruction, the operand format is R1,D2(X2,B2)

 

Table of Contents Previous Section Next Section D, Divide

Operand-1 (r1) is an even/odd pair of registers (dividend) that is divided by the value at the storage location specified by operand-2 (x2+b2+d2).

The remainder is put in r1-even and the quotient is put in r1-odd.

           
   
   
 
 
X2=index
   
   
   
   
B2=base register
D2=displacement
   
5D
RX
BDDD
D R1,D2(X2,B2)
R1=register
 
 
   
   
Condition Code
The code remains unchanged.
 
D, Divide Instruction, the operand format is R1,D2(X2,B2)

 

Table of Contents Previous Section Next Section DP, Divide Packed (Decimal)

The data string located at the storage address specified by operand-1 (b1+d1) is divided by the data string located at the storage address specified by operand-2 (b2+d2).

Operand-2 remains unchanged.

               
   
   
 
 
 
 
L2=length
   
   
   
   
B2=base register
D2=displacement
   
FD
LL
BDDD
BDDD
DP D1(L1,B1),D2(L2,B2)
   
L1=length
 
 
   
   
   
   
B1=base register
D1=displacement
 
 
 
 
   
   
Condition Code
The code remains unchanged.
 
DP, Divide Packed (Decimal) Instruction, the operand format is D1(L1,B1),D2(L2,B2)

 

Table of Contents Previous Section Next Section DR, Divide Registers

The registers specified by operand-1 (r1) are an even/odd pair of registers (dividend) and the value is divided by operand-2 (r2). The remainder is put in r1-even and the quotient is put in r1-odd.

           
   
   
R2=register
1D
RR
DR R1,R2
R1=register
 
 
   
   
Condition Code
The code remains unchanged.
 
DR, Divide Registers Instruction, the operand format is R1,R2

 

Table of Contents Previous Section Next Section ED, Edit

The data string located at the storage address specified by operand-2 (b2+d2) is integrated with the data string at the storage address specified by operand-1.

Operand-2 (b2+d2) remains unchanged. Operand-1 should be initialized with an edit word.

The length is determined by the length specified in the 2nd byte of the Edit instruction. The length field applies to the edit word or pattern (the first operand).

               
LL=length
from x'00' to x'FF'
 
 
   
   
   
   
B2=base register
D2=displacement
   
DE
LL
BDDD
BDDD
ED D1(L,B1),D2(B2)
   
B1=base register
D1=displacement
 
 
 
 
   
   
Condition Code
0 - result field = zero
1 - result field < zero
2 - result field > zero
3 - --
 
ED, Edit Instruction, the operand format is D1(L,B1),D2(B2)

 

Table of Contents Previous Section Next Section EDMK, Edit and Mark

The data string located at the storage address specified by operand-2 (b2+d2) is integrated with the data string at the storage address specified by operand-1.

The instruction is identical to ED (or Edit) instruction, except for the additional function of inserting a byte address in general register 1.

Operand-2 (b2+d2) remains unchanged. Operand-1 should be initialized with an edit word.

The length is determined by the length specified in the 2nd byte of the Edit instruction. The length field applies to the edit word or pattern (the first operand).

               
LL=length
from x'00' to x'FF'
 
 
   
   
   
   
B2=base register
D2=displacement
   
DF
LL
BDDD
BDDD
EDMK D1(L,B1),D2(B2)
   
B1=base register
D1=displacement
 
 
 
 
   
   
Condition Code
0 - result field = zero
1 - result field < zero
2 - result field > zero
3 - --
 
EDMK, Edit and Mark Instruction, the operand format is D1(L,B1),D2(B2)

 

Table of Contents Previous Section Next Section EX, Execute

The instruction at the address specified by operand-2 (x2+b2+d2) is modified then executed using the contents of operand-1 (r1). Bits 8-15 of operand-1 and bits 24-31 of operand-1 are OR'ed together.

           
   
   
 
 
X2=index
   
   
   
   
B2=base register
D2=displacement
   
44
RX
BDDD
EX R1,D2(X2,B2)
R1=register
 
 
   
   
Condition Code
The code remains unchanged.
 
EX, Execute Instruction, the operand format is R1,D2(X2,B2)

 

Table of Contents Previous Section Next Section IC, Insert Characters

The byte at the address specified by operand-2 (x2+b2+d2) is inserted into bit positions 24-31 of operand-1 (r1).

           
   
   
 
 
X2=index
   
   
   
   
B2=base register
D2=displacement
   
43
RX
BDDD
IC R1,D2(X2,B2)
R1=register
 
 
   
   
Condition Code
The code remains unchanged.
 
IC, Insert Character Instruction, the operand format is R1,D2(X2,B2)

 

Table of Contents Previous Section Next Section ICM, Insert Character under Mask

Bytes from storage location specified by operand-2 (b2+d2) are inserted into operand-1 (r1) under control of the mask (m3).

           
R1=register
 
 
   
   
   
   
   
B2=base register
D2=displacement
   
BF
RM
BDDD
ICM R1,M3,D2(B2)
M3=mask
 
 
   
   
Condition Code
The code remains unchanged.
 
ICM, Insert Character under Mask Instruction, the operand format is R1,M3,D2(B2)

 

Table of Contents Previous Section Next Section L, Load

The four bytes at the storage address specified by operand-2 (x2+b2+d2) are loaded into the register specified by operand-1 (r1).

           
   
   
 
 
X2=index
   
   
   
   
B2=base register
D2=displacement
   
58
RX
BDDD
L R1,D2(X2,B2)
R1=register
 
 
   
   
Condition Code
The code remains unchanged.
 
L, Load Instruction, the operand format is R1,D2(X2,B2)

 

Table of Contents Previous Section Next Section LA, Load Address

The address of operand-2 (x2+b2+d2) is loaded into the register specified by operand-1 (r1).

           
   
   
 
 
X2=index
   
   
   
   
B2=base register
D2=displacement
   
41
RX
BDDD
LA R1,D2(X2,B2)
R1=register
 
 
   
   
Condition Code
The code remains unchanged.
 
LA, Load Address Instruction, the operand format is R1,D2(X2,B2)

 

Table of Contents Previous Section Next Section LCR, Load Complement Registers

The two's complement of operand-2 (r2) is put into operand-1 (r1). For example, if the register specified by operand-2 contained x'00000010' then after the LCR instruction was executed the register specified by operand-1 would contain x'FFFFFFF0'.

         
   
   
R2=register
13
RR
LCM R1,R2
R1=register
 
 
   
   
Condition Code
  The code remains unchanged.
 
LCR, Load Complement Registers Instruction, the operand format is R1,R2

 

Table of Contents Previous Section Next Section LH, Load Halfword

The two bytes (halfword) located at the storage address specified by operand-2 (x2+b2+d2) is loaded into the rightmost two bytes (bits 16-31) of the register specified by operand-1 (r1).

           
   
   
 
 
X2=index
   
   
   
   
B2=base register
D2=displacement
   
48
RX
BDDD
LH R1,D2(X2,B2)
R1=register
 
 
   
   
Condition Code
The code remains unchanged.
 
LH, Load Halfword Instruction, the operand format is R1,D2(X2,B2)

 

Table of Contents Previous Section Next Section LM, Load Multiples

The set of registers starting with operand-1 (r1) and ending with (r3) are loaded from the storage location specified by operand-2 (b2+d2).

           
R1=register
 
 
   
   
   
   
   
   
B2=base register
D2=displacement
   
98
RR
BDDD
LM R1,D2(R3,B2)
R3=register
 
 
   
   
Condition Code
The code remains unchanged.
 
LM, Load Multiples Instruction, the operand format is R1,D2(R3,B2)

 

Table of Contents Previous Section Next Section LNR, Load Negative Registers

The two's complement of the absolute value of operand-2 (r2) is put into operand-1 (r1).

         
   
   
R2=register
11
RR
LNR R1,R2
R1=register
 
 
   
   
Condition Code
  The code remains unchanged.
 
LNR, Load Negative Registers Instruction, the operand format is R1,R2

 

Table of Contents Previous Section Next Section LPR, Load Positive Registers

The absolute value of operand-2 (r2) is put into operand-1 (r1).

         
   
   
R2=register
10
RR
LPR R1,R2
R1=register
 
 
   
   
Condition Code
  The code remains unchanged.
 
LPR, Load Positive Registers Instruction, the operand format is R1,R2

 

Table of Contents Previous Section Next Section LR, Load Register

The value of operand-2 (r2) is put into operand-1 (r1).

         
   
   
R2=register
18
RR
LR R1,R2
R1=register
 
 
   
   
Condition Code
  The code remains unchanged.
 
LR, Load Registers Instruction, the operand format is R1,R2

 

Table of Contents Previous Section Next Section LTR, Load and Test Register

Operand-2 (r2) is put into operand-1 (r1). The sign and magnitude of operand-2 (r2), treated as a 32-bit signed binary integer are indicated in the condition code.

         
   
   
R2=register
12
RR
LTR R1,R2
R1=register
 
 
   
   
Condition Code
  0 - result = zero
  1 - result < zero
  2 - result > zero
  3 - --
 
LTR, Load and Test Register Instruction, the operand format is R1,R2

 

Table of Contents Previous Section Next Section M, Multiply

The value located at the storage address specified by operand-2 (x2+b2+d2) is multiplied with the 2nd-word (i.e. the second register of the pair) of operand-1 (r1). The doubleword product is put in operand-1.

           
   
   
 
 
X2=index
   
   
   
   
B2=base register
D2=displacement
   
5C
RX
BDDD
M R1,D2(X2,B2)
R1=register
 
 
   
   
Condition Code
The code remains unchanged
 
M, Multiply Instruction, the operand format is R1,D2(X2,B2)

 

Table of Contents Previous Section Next Section MH, Multiply Halfword

The value located at the storage address specified by operand-2 (x2+b2+d2) is multiplied with operand-1 (r1). The product is put in operand-1.

           
   
   
 
 
X2=index
   
   
   
   
B2=base register
D2=displacement
   
4C
RX
BDDD
MH R1,D2(X2,B2)
R1=register
 
 
   
   
Condition Code
The code remains unchanged
 
MH, Multiply Halfword Instruction, the operand format is R1,D2(X2,B2)

 

Table of Contents Previous Section Next Section MP, Multiply Packed (Decimal)

The product of the data string located at the storage address specified by operand-2 (B2+D2) and the data string located at the storage address specified by operand-1 (B1+D1) is placed in the operand-1 location. Operand-2 remains unchanged.

The operands may be different lengths with a maximum length of 16 bytes (or 31 digits since this is packed) for each operand. The condition code is set as shown below.

               
   
   
 
 
 
 
L2=length
   
   
   
   
B2=base register
D2=displacement
   
FC
LL
BDDD
BDDD
MP D1(L1,B1),D2(L2,B2)
   
L1=length
 
 
   
   
   
   
B1=base register
D1=displacement
 
 
 
 
   
   
Condition Code
0 - op1 = 0, n/o
1 - op1 < 0, n/o
2 - op1 > 0, n/o
3 - overflow
 
MP, Multiply Packed (Decimal) Instruction, the operand format is D1(L1,B1),D2(L2,B2)

 

Table of Contents Previous Section Next Section MR, Multiply Registers

The second word (odd-register) of operand-1 (r1) is multiplied by operand-2 (r2), the doubleword product is put in operand-1 (r1, even/odd-pair).

         
   
   
R2=register
1C
RR
MR R1,R2
R1=register
 
 
   
   
Condition Code
The code remains unchanged.
 
MR, Multiply Registers Instruction, the operand format is R1,R2

 

Table of Contents Previous Section Next Section MVC, Move Characters

The data string located at the storage address specified by operand-2 (b2+d2) is moved to the storage address specified by operand-1 (b1+d1).

Operand-2 remains unchanged. The number of bytes moved is determined by the length specified in the 2nd byte of the MVC instruction.

               
LL=length
from x'00' to x'FF'
 
 
   
   
   
   
B2=base register
D2=displacement
   
D2
LL
BDDD
BDDD
MVC D1(L,B1),D2(B2)
   
B1=base register
D1=displacement
 
 
 
 
   
   
Condition Code
The code remains unchanged
 
MVC, Move Characters Instruction, the operand format is D1(L,B1),D2(B2)

 

Table of Contents Previous Section Next Section MVCIN, Move Characters Inverse

The data string located at the storage address specified by operand-2 (b2+d2) is moved to the storage address specified by operand-1 (b1+d1) with the left-to-right sequence of the bytes inverted.

Operand-2 remains unchanged. The number of bytes moved is determined by the length specified in the 2nd byte of the MVC instruction.

               
LL=length
from x'00' to x'FF'
 
 
   
   
   
   
B2=base register
D2=displacement
   
E8
LL
BDDD
BDDD
MVCIN D1(L,B1),D2(B2)
   
B1=base register
D1=displacement
 
 
 
 
   
   
Condition Code
The code remains unchanged
 
MVCIN, Move Characters Inverse Instruction, the operand format is D1(L,B1),D2(B2)

 

Table of Contents Previous Section Next Section MVCL, Move Characters Long

The data string identified by operand-2 (R2) is moved to the storage location identified by operand-1 (R1). Both operands are register-pairs.

The first register of each operand needs to be loaded with the storage addresses of the data strings. The second register of each operand needs to be loaded with the length of each operand.

The data strings may be different length. The high-order byte of the second register of operand-2 is treated as the padding character if the operands or different lengths.

The move proceeds from left to right, low storage to high storage and as each character is moved the length registers are decremented.

           
   
   
R2=register-pair
0E
RR
MVCL R1,R2
R1=register-pair
 
 
   
   
Condition Code
0 - equal
1 - op1 is low
2 - op1 is high
3 -  
 
MVCL, Move Characters Long Instruction, the operand format is R1,R2

 

Table of Contents Previous Section Next Section MVI, Move Immediate

Operand-2 (the immediate data that is the second byte of the instruction itself) is moved to the storage address specifed by operand-1 (b1+d1).

           
   
   
B1=base register
D1=displacement
   
92
II
BDDD
MVI D1(B1),I2
I2=immediate
 
 
   
   
Condition Code
The code remains unchanged
 
MVI, Move Immediate Instruction, the operand format is D1(B1),I2

 

Table of Contents Previous Section Next Section MVN, Move Numerics

The rightmost 4-bits of each byte of the data string located at the storage address specified by operand-2 (b2+d2) are put into the storage address specified by operand-1 (b1+d1).

Operand-2 remains unchanged. The length is determined by the value in the 2nd byte of the MVN instruction.

               
LL=length
from x'00' to x'FF'
 
 
   
   
   
   
B2=base register
D2=displacement
   
D1
LL
BDDD
BDDD
MVN D1(L,B1),D2(B2)
   
B1=base register
D1=displacement
 
 
 
 
   
   
Condition Code
The code remains unchanged
 
MVN, Move Numerics Instruction, the operand format is D1(L,B1),D2(B2)

 

Table of Contents Previous Section Next Section MVO, Move with Offset

The data string located at the storage address specified by operand-2 (b2+d2) is shifted left four bits and put into the storage address specified by operand-1 (b1+d1). The rightmost 4-bits of operand-1 remain unchanged.

               
   
   
 
 
 
 
L2=length
   
   
   
   
B2=base register
D2=displacement
   
F1
LL
BDDD
BDDD
MVO D1(L1,B1),D2(L2,B2)
   
L1=length
 
 
   
   
   
   
B1=base register
D1=displacement
 
 
 
 
   
   
Condition Code
The code remains unchanged
 
MVO, Move with Offset Instruction, the operand format is D1(L1,B1),D2(L2,B2)

 

Table of Contents Previous Section Next Section MVZ, Move Zones

The lefmost 4-bits of each byte of the data string located at the storage address specified by operand-2 (b2+d2) are put into the storage address specified by operand-1 (b1+d1).

Operand-2 remains unchanged. The length is determined by the value in the 2nd byte of the MVZ instruction.

               
LL=length
from x'00' to x'FF'
 
 
   
   
   
   
B2=base register
D2=displacement
   
D3
LL
BDDD
BDDD
MVZ D1(L,B1),D2(B2)
   
B1=base register
D1=displacement
 
 
 
 
   
   
Condition Code
The code remains unchanged
 
MVZ, Move Zones Instruction, the operand format is D1(L,B1),D2(B2)

 

Table of Contents Previous Section Next Section N, And

The content of operand-1 (r1) is AND'ed with the data string located at the storage address specified by operand-2 (x2+b2+d2).

The results of the AND'ing process is put into operand-1.

           
   
   
 
 
X2=index
   
   
   
   
B2=base register
D2=displacement
   
54
RX
BDDD
N R1,D2(X2,B2)
R1=register
 
 
   
   
Condition Code
0 -result-is-zero
1 - result-not-zero
2 - --
3 - --
 
N, And Instruction, the operand format is R1,D2(X2,B2)

 

Table of Contents Previous Section Next Section NC, And Characters

The data string located at the storage address specified by operand-1 (b1+d1) is AND'ed with the data string located at the storage address specified by operand-2 (b2+d2).

The results of the exclusive AND'ing process is put into operand-1.

               
LL=length
from x'00' to x'FF'
 
 
   
   
   
   
B2=base register
D2=displacement
   
D4
LL
BDDD
BDDD
NC D1(L,B1),D2(B2)
   
B1=base register
D1=displacement
 
 
 
 
   
   
Condition Code
0 - result-is-zero
1 - result-not-zero
2 - --
3 - --
 
NC, And Characters Instruction, the operand format is D1(L,B1),D2(B2)

 

Table of Contents Previous Section Next Section NI, And Immediate

The data string located at the storage address specified by operand-1 (b1+d1) is AND'ed with operand-2 (i2 is immediate data included as the second byte of the instruction itself).

The results of the AND'ing process is put into operand-1.

           
   
   
B1=base register
D1=displacement
   
94
II
BDDD
NI D1(B1),I2
I2=immediate
 
 
   
   
Condition Code
0 - result-is-zero
1 - result-not-zero
2 - --
3 - --
 
NI, And Immediate Instruction, the operand format is D1(B1),I2

 

Table of Contents Previous Section Next Section NR, And Registers

The content of operand-1 (r1) is AND'ed with the content of operand-2 (r2). The results of the AND'ing process is put into operand-1.

           
   
   
R2=register
14
RR
NR R1,R2
R1=register
 
 
   
   
Condition Code
0 - result-is-zero
1 - result-not-zero
2 - --
3 - --
 
NR, And Registers Instruction, the operand format is R1,R2

 

Table of Contents Previous Section Next Section O, Or

The content of operand-1 (r1) is OR'ed with the data string located at the storage address specified by operand-2 (x2+b2+d2).

The results of the OR'ing process is put into operand-1.

           
   
   
 
 
X2=index
   
   
   
   
B2=base register
D2=displacement
   
56
RX
BDDD
O R1,D2(X2,B2)
R1=register
 
 
   
   
Condition Code
0 -result-is-zero
1 - result-not-zero
2 - --
3 - --
 
O, Or Instruction, the operand format is R1,D2(X2,B2)

 

Table of Contents Previous Section Next Section OC, Or Characters

The data string located at the storage address specified by operand-1 (b1+d1) is OR'ed with the data string located at the storage address specified by operand-2 (b2+d2).

The results of the OR'ing process is put into operand-1.

               
LL=length
from x'00' to x'FF'
 
 
   
   
   
   
B2=base register
D2=displacement
   
D6
LL
BDDD
BDDD
OC D1(L,B1),D2(B2)
   
B1=base register
D1=displacement
 
 
 
 
   
   
Condition Code
0 - result-is-zero
1 - result-not-zero
2 - --
3 - --
 
OC, Or Characters Instruction, the operand format is D1(L,B1),D2(B2)

 

Table of Contents Previous Section Next Section OI, Or Immediate

The data string located at the storage address specified by operand-1 (b1+d1) is OR'ed with operand-2 (i2 is immediate data included as the second byte of the instruction itself).

The results of the OR'ing process is put into operand-1.

           
   
   
B1=base register
D1=displacement
   
96
II
BDDD
OI D1(B1),I2
I2=immediate
 
 
   
   
Condition Code
0 - result-is-zero
1 - result-not-zero
2 - --
3 - --
 
OI, Or Immediate Instruction, the operand format is D1(B1),I2

 

Table of Contents Previous Section Next Section OR, Or Registers

The content of operand-1 (r1) is OR'ed with the content of operand-2 (r2). The results of the OR'ing process is put into operand-1.

           
   
   
R2=register
16
RR
OR R1,R2
R1=register
 
 
   
   
Condition Code
0 - result-is-zero
1 - result-not-zero
2 - --
3 - --
 
OR, Or Registers Instruction, the operand format is R1,R2

 

Table of Contents Previous Section Next Section PACK, Pack

The data string located at the storage address specified by operand-2 (b2+d2) is changed from zoned-decimal to packed and the result is put into the storage address specified by operand-1 (b1+d1).

Operand-2 remains unchanged. The operands may be different lengths with a maximum length of 16 bytes (or 31 digits since this is packed) for each operand.

               
   
   
 
 
 
 
L2=length
   
   
   
   
B2=base register
D2=displacement
   
F2
LL
BDDD
BDDD
PACK D1(L1,B1),D2(L2,B2)
   
L1=length
 
 
   
   
   
   
B1=base register
D1=displacement
 
 
 
 
   
   
Condition Code
The code remains unchanged.
 
PACK, Pack (Decimal) Instruction, the operand format is D1(L1,B1),D2(L2,B2)

 

Table of Contents Previous Section Next Section S, Subtract

The full word (4 bytes) located at the storage address specified by operand-2 (X2+B2+D2} is subtracted from a value that is stored in the register specified by operand-1(R1). Operand-2 remains unchanged. The condition code is set as shown below.

           
   
   
 
 
X2=index
   
   
   
   
B2=base register
D2=displacement
   
5B
RX
BDDD
S R1,D2(X2,B2)
R1=register
 
 
   
   
Condition Code
0 - op1 = 0, n/o
1 - op1 < 0, n/o
2 - op1 > 0, n/o
3 - overflow
 
S, Subtract Instruction, the operand format is R1,D2(X2,B2)

 

Link to Internet   Link to Server   Explore the RX Format of the Subtract Instruction. The assembler program is written to comply with an Assembler/H or HLASM Mainframe Assembler dialect. A JCL member is provided as a job script to run as a batch job on an IBM Mainframe System with ZOS or a Windows System with Micro Focus Enterprise Developer.

Table of Contents Previous Section Next Section SH, Subtract Halfword

The half word (2 bytes) located at the storage address specified by operand-2 (x2+b2+d2) is subtracted from the register specified by operand-1 (r1). Operand-2 remains unchanged. The condition code is set as shown below.

           
   
   
 
 
X2=index
   
   
   
   
B2=base register
D2=displacement
   
4B
RX
BDDD
SH R1,D2(X2,B2)
R1=register
 
 
   
   
Condition Code
0 - op1 = 0, n/o
1 - op1 < 0, n/o
2 - op1 > 0, n/o
3 - overflow
 
SH, Subtract Halfword Instruction, the operand format is R1,D2(X2,B2)

 

Table of Contents Previous Section Next Section SL, Subtract Logical

The full word (4 bytes) located at the storage address specified by operand-2 (x2+b2+d2) is subtracted from the register specified by operand-1 (r1). Operand-2 remains unchanged. The condition code is set as shown below.

           
   
   
 
 
X2=index
   
   
   
   
B2=base register
D2=displacement
   
5F
RX
BDDD
SL R1,D2(X2,B2)
R1=register
 
 
   
   
Condition Code
0 - zero, no-carry
1 - not-zero, no-carry
2 - zero, carry
3 - not-zero, carry
 
SL, Subtract Logical Instruction, the operand format is R1,D2(X2,B2)

 

Table of Contents Previous Section Next Section SLA, Shift Left Single

The 31-bit numeric part (bit-0 is the sign and bits 1-31 are the numerics) of operand-1 (r1) is shifted left the number of bits specified by operand-2 (b2+d2).

With this instruction operand-2 (b2+d2) does not address storage. Bits 0-25 are ignored, bits 26-31 specify the number of bit positions to be shifted.

           
   
   
 
 
0=not used
   
   
   
   
B2=base register
D2=displacement
   
8B
R0
BDDD
SLA R1,D2(X2,B2)
R1=register
 
 
   
   
Condition Code
0 - op1=0, n/o
1 - op1<0, n/o
2 - op1>0, n/o
3 - overflow
 
SLA, Shift Left Single Instruction, the operand format is R1,D2(X2,B2)

 

Table of Contents Previous Section Next Section SLDA, Shift Left Double

With this instruction operand-2 (b2+d2) does not address storage. Bits 0-25 are ignored, bits 26-31 specify the number of bit positions to be shifted.

Note: If an ODD/EVEN pair of registers is specified then an 0C6 error will occur

           
   
   
 
 
0=not used
   
   
   
   
B2=base register
D2=displacement
   
8F
R0
BDDD
SLDA R1,D2(X2,B2)
R1=even-odd pair
 
 
   
   
Condition Code
0 - op1=0, n/o
1 - op1<0, n/o
2 - op1>0, n/o
3 - overflow
 
SLDA, Shift Left Double Instruction, the operand format is R1,D2(X2,B2)

 

Table of Contents Previous Section Next Section SLDL, Shift Left Double Logical

The 64-bits of operand-1 (r1 is an EVEN/ODD pair of registers) is shifted left the number of bits specified by operand-2 (b2+d2).

With this instruction operand-2 (b2+d2) does not address storage. Bits 0-25 are ignored, bits 26-31 specify the number of bit positions to be shifted.

Note: If an ODD/EVEN pair of registers is specified then an 0C6 error will occur

           
   
   
 
 
0=not used
   
   
   
   
B2=base register
D2=displacement
   
8D
R0
BDDD
SLDL R1,D2(X2,B2)
R1=even-odd pair
 
 
   
   
Condition Code
0 - op1=0, n/o
1 - op1<0, n/o
2 - op1>0, n/o
3 - overflow
 
SLDL, Shift Left Double Logical Instruction, the operand format is R1,D2(X2,B2)

 

Table of Contents Previous Section Next Section SLL, Shift Left Single Logical

The 32-bits of operand-1 (r1) is shifted left the number of bits specified by operand-2 (b2+d2).

With this instruction operand-2 (b2+d2) does not address storage. Bits 0-25 are ignored, bits 26-31 specify the number of bit positions to be shifted.