370 Instructions
 Problem-State
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  Table of Contents Version 09.05.17 
  Introduction
  Instruction List sequenced by Mnemonic Opcode
 
  Quick link by alphabet:   A | B | C | D | E | I | L | M | N | O | P | S | T | U | X | Z | Extended Mnemonics for Branching
  Instruction List sequenced by Hexadecimal Opcode
  Instruction Overview
  Summary
 
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Introduction
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This document is intended to be used as a quick reference for the mainframe, problem-state, non-floating point instructions. The source code for the sample program that executes each of the problem-state, non-floating point instructions provides additional detail.

Instruction List sequenced by Mnemonic Opcode
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The following list is sequenced by the Mnemonic Opcode.

  Instruction Mnemonic  Hex  Format
  Add A 5A R1,D2(X2,B2)
  Add Halfword AH 4A R1,D2(X2,B2)
  Add Logical AL 5E R1,D2(X2,B2)
  Add Logical Registers ALR 1E R1,R2
  Add Packed (Decimal) AP FA D1(L1,B1),D2(L2,B2)
  Add Registers AR 1A R1,R2
  Branch and Link BAL 45 R1,D2(X2,B2)
  Branch and Link Register BALR 05 R1,R2
  Branch and Save BAS 4D R1,D2(X2,B2)
  Branch and Save Register BASM 0D R1,R2
  Branch, Save and Set Mode BASSM 0C R1,R2
  Branch on Condition BC 47 M1,D2(X2,B2)
  Branch on Condition Register BCR 07 M1,R2
  Branch on Count BCT 46 R1,D2((X2,B2)
  Branch on Count Register BCTR 06 R1,R2
  Branch and Set Mode BSM 0B R1,R2
  Branch on Index High BXH 86 R1,R3,D2(B2)
  Branch on Index Low/Equal BXLE 87 R1,R3,D2(B2)
  Compare C 59 R1,D2(X2,B2)
  Compare Double and Swap CDS BB R1,R3,D29B2)
  Compare Halfword CH 49 R1,D2(X2,B2)
  Compare Logical CL 55 R1,D2(X2,B2)
  Compare Logical Characters CLC D5 D1(L,B1),D2(B2)
  Compare Logical Characters Long  CLCL 0F R1,R2
  Compare Logical Immediate CLI 95 D1(B1),I2
  Compare Logical under Mask CLM BD R1,M3,D2(B2)
  Compare Logical Registers CLR 15 R1,R2
  Compare Packed (Decimal) CP F9 D1(L1,B1),D2(L2,B2)
  Compare Registers CR 19 R1,R2
  Compare and Swap CS BA R1,R3,D2(B2)
  Convert to Binary CVB 4F R1,D2((X2,B2)
  Convert to Decimal CVD 4E R1,D2((X2,B2)
  Divide D 5D R1,D2((X2,B2)
  Divide Packed (Decimal) DP FD D1(L1,B1),D2(L2,B2)
  Divide Registers DR 1D R1,R2
  Edit ED DE D1(L1,B1),D2(B2)
  Edit and Mark EDMK DF D1(L1,B1),D2(B2)
  Execute EX 44 R1,D2(X2,B2)
  Insert Character IC 43 R1,D2(X2,B2)
  Insert Character under Mask ICM BF R1,M3,D2(B2)
  Load L 58 R1,D2(X2,B2)
  Load Address LA 41 R1,D2(X2,B2)
  Load Complement Registers LCR 13 R1,R2
  Load Halfword LH 48 R1,D2(X2,B2)
  Load Multiple LM 98 R1,R3,D2(B2)
  Load Negative LNR 11 R1,R2
  Load Postive LPR 10 R1,R2
  Load Register LR 18 R1,R2
  Load and Test Register LTR 12 R1,R2
  Multipy M 5C R1,D2(X2,B2)
  Multipy Halfword MH 4C R1,D2(X2,B2)
  Multipy Packed (Decimal) MP FC D1(L1,B1),D2(L2,B2) 
  Multipy Registers MR 1C R1,R2
  Move Characters MVC D2 D1(L,B1),D2(B2)
  Move Inverse MVCIN E8 D1(L,B1),D2(B2)
  Move Characters Long MVCL 0E R1,R2
  Move Immediate MVI 92 D1(B1),I2
  Move Numerics MVN D1 D1(L,B1),D2(B2)
  Move with Offset MVO F1 D1(L1,B1),D2(L2,B2)
  Move Zones MVZ D3 D1(L,B1),D2(B2)
  aNd N 54 R1,D2(X2,B2)
  aNd Characters NC D4 D1(L,B1),D2(B2)
  aNd Immediate NI 94 D1(B1),I2
  aNd Registers NR 14 R1,R2
  Or O 56 R1,D2(X2,B2)
  Or Characters OC D6 D1(L,B1),D2(B2)
  Or Immediate OI 96 D1(B1),I2
  Or Registers OR 16 R1,R2
  Pack PACK F2 D1(L1,B1),D2(L2,B2)
  Subtract S 5B R1,D2(X2,B2)
  Subtract Halfword SH 4B R1,D2(X2,B2)
  Subtract Logical SL 5F R1,D2(X2,B2)
  Shift Left Single SLA 8B R1,D2(B2)
  Shift Left Double SLDA 8F R1,D2(B2)
  Shift Left Double Logical SLDL 8D R1,D2(B2)
  Shift Left Single Logical SLL 89 R1,D2(B2)
  Subtract Logical Registers SLR 1F R1,R2
  Subtract Packed (Decimal) SP FB D1(L1,B1),D2(L2,B2)
  Subtract Registers SR 1B R1,R2
  Shift Right Single SRA 8A R1,D2(B2)
  Shift Right Double SRDA 8E R1,D2(B2)
  Shift Right Double Logical SRDL 8C R1,D2(B2)
  Shift Right Single Logical SRL 88 R1,D2(B2)
  Shift and Round Decimal SRP F0 D1(L1,B1),D2(B2),I3 
  Store ST 50 R1,D2(X2,B2)
  Store Character STC 42 R1,D2(X2,B2)
  Store Character under Mask STCM BE R1,M3,D2(B2)
  Store Halfword STH 40 R1,D2(X2,B2)
  Store Multiple STM 90 R1,R3,D2(B2)
  Supervisor Call SVC 0A I1
  Test under Mask TM 91 D1(B1),I2
  Translate TR DC D1(L1,B1),D2(B2)
  Translate and Test TRT DD D1(L1,B1),D2(B2)
  Unpack UNPK F3 D1(L1,B1),D2(L2,B2)
  eXclusive Or X 57 R1,D2(X2,B2)
  eXclusive Or Characters XC D7 D1(L,B1),D2(B2)
  eXclusive Or Immediate XI 97 D1(B1),I2
  eXclusive Or Registers XR 17 R1,R2
  Zero Add Packed ZAP F8 D1(L1,B1),D2(L2,B2)

Instruction List sequenced by Hexadecimal Opcode
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The following list is sequenced by the Hexadecimal Opcode.

  Instruction Mnemonic  Hex  Format
  Branch and Link Register BALR 05 R1,R2
  Branch on Count Register BCTR 06 R1,R2
  Branch on Condition Register BCR 07 M1,R2
  Supervisor Call SVC 0A I1
  Branch and Set Mode BSM 0B R1,R2
  Branch, Save and Set Mode BASSM 0C R1,R2
  Branch and Save Register BASM 0D R1,R2
  Move Characters Long MVCL 0E R1,R2
  Compare Logical Characters Long  CLCL 0F R1,R2
  Load Postive LPR 10 R1,R2
  Load Negative LNR 11 R1,R2
  Load and Test Register LTR 12 R1,R2
  Load Complement Registers LCR 13 R1,R2
  aNd Registers NR 14 R1,R2
  Compare Logical Registers CLR 15 R1,R2
  Or Registers OR 16 R1,R2
  eXclusive Or Registers XR 17 R1,R2
  Load Register LR 18 R1,R2
  Compare Registers CR 19 R1,R2
  Add Registers AR 1A R1,R2
  Subtract Registers SR 1B R1,R2
  Multipy Registers MR 1C R1,R2
  Divide Registers DR
1D R1,R2
  Add Logical Registers ALR 1E R1,R2
  Subtract Logical Registers SLR 1F R1,R2
  Store Halfword STH 40 R1,D2(X2,B2)
  Load Address LA 41 R1,D2(X2,B2)
  Store Character STC 42 R1,D2(X2,B2)
  Insert Character IC 43 R1,D2(X2,B2)
  Execute EX 44 R1,D2(X2,B2)
  Branch and Link BAL 45 R1,D2(X2,B2)
  Branch on Count BCT 46 R1,D2((X2,B2)
  Branch on Condition BC 47 M1,D2(X2,B2)
  Load Halfword LH 48 R1,D2(X2,B2)
  Compare Halfword CH 49 R1,D2(X2,B2)
  Add Halfword AH 4A R1,D2(X2,B2)
  Subtract Halfword SH 4B R1,D2(X2,B2)
  Multipy Halfword MH 4C R1,D2(X2,B2)
  Branch and Save BAS 4D R1,D2(X2,B2)
  Convert to Decimal CVD 4E R1,D2((X2,B2)
  Convert to Binary CVB 4F R1,D2((X2,B2)
  Store STb 50 R1,D2(X2,B2)
  aNd N 54 R1,D2(X2,B2)
  Compare Logical CL 55 R1,D2(X2,B2)
  Or O 56 R1,D2(X2,B2)
  eXclusive Or X 57 R1,D2(X2,B2)
  Load L 58 R1,D2(X2,B2)
  Compare C 59 R1,D2(X2,B2)
  Add A 5A R1,D2(X2,B2)
  Subtract S 5B R1,D2(X2,B2)
  Multipy M 5C R1,D2(X2,B2)
  Divide D 5D R1,D2((X2,B2)
  Add Logical AL 5E R1,D2(X2,B2)
  Subtract Logical SL 5F R1,D2(X2,B2)
  Branch on Index High BXH 86 R1,R3,D2(B2)
  Branch on Index Low/Equal BXLE 87 R1,R3,D2(B2)
  Shift Right Single Logical SRL 88 R1,D2(B2)
  Shift Left Single Logical SLL 89 R1,D2(B2)
  Shift Right Single SRA 8A R1,D2(B2)
  Shift Left Single SLA 8B R1,D2(B2)
  Shift Right Double Logical SRDL 8C R1,D2(B2)
  Shift Left Double Logical SLDL 8D R1,D2(B2)
  Shift Right Double SRDA 8E R1,D2(B2)
  Shift Left Double SLDA 8F R1,D2(B2)
  Store Multiple STM 90 R1,R3,D2(B2)
  Test under Mask TM 91 D1(B1),I2
  Move Immediate MVI 92 D1(B1),I2
  aNd Immediate NI 94 D1(B1),I2
  Compare Logical Immediate CLI 95 D1(B1),I2
  Or Immediate OI 96 D1(B1),I2
  eXclusive Or Immediate XI 97 D1(B1),I2
  Load Multiple LM 98 R1,R3,D2(B2)
  Compare and Swap CS BA R1,R3,D2(B2)
  Compare Double and Swap CDS BB R1,R3,D29B2)
  Compare Logical under Mask CLM BD R1,M3,D2(B2)
  Store Character under Mask STCM BE R1,M3,D2(B2)
  Insert Character under Mask ICM BF R1,M3,D2(B2)
  Move Numerics MVN D1 D1(L,B1),D2(B2)
  Move Characters MVC D2 D1(L,B1),D2(B2)
  Move Zones MVZ D3 D1(L,B1),D2(B2)
  aNd Characters NC D4 D1(L,B1),D2(B2)
  Compare Logical Characters CLC D5 D1(L,B1),D2(B2)
  Or Characters OC D6 D1(L,B1),D2(B2)
  eXclusive Or Characters XC D7 D1(L,B1),D2(B2)
  Translate TR DC D1(L1,B1),D2(B2)
  Translate and Test TRT DD D1(L1,B1),D2(B2)
  Edit ED DE D1(L1,B1),D2(B2)
  Edit and Mark EDMK DF D1(L1,B1),D2(B2)
  Move Inverse MVCIN E8 D1(L,B1),D2(B2)
  Shift and Round Decimal SRP F0 D1(L1,B1),D2(B2),I3 
  Move with Offset MVO F1 D1(L1,B1),D2(L2,B2)
  Pack PACK F2 D1(L1,B1),D2(L2,B2)
  Unpack UNPK F3 D1(L1,B1),D2(L2,B2)
  Zero Add Packed ZAP F8 D1(L1,B1),D2(L2,B2)
  Compare Packed (Decimal) CP F9 D1(L1,B1),D2(L2,B2)
  Add Packed (Decimal) AP FA D1(L1,B1),D2(L2,B2)
  Subtract Packed (Decimal) SP FB D1(L1,B1),D2(L2,B2)
  Multipy Packed (Decimal) MP FC D1(L1,B1),D2(L2,B2) 
  Divide Packed (Decimal) DP FD D1(L1,B1),D2(L2,B2)

Instruction Overview
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This program may serve as a tutorial for programmers that are new to 370 assembler or as a reference for experienced programmers.

A, Add
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The full word (4 bytes) located at the storage address specified by operand-2 (x2+b2+d2} is added to the register specified by operand-1(r1). Operand-2 remains unchanged. The condition code is set as shown below.

   
 
     
     
     
     
     
     
x2=index
b2=base register
ddd2=displacement
 
   
5A RX BDDD
   
 
r1=register
 
 
 
     
     
     
 
  Condition Code
0 - op1=0, n/o
1 - op1<0, n/o
2 - op1>0, n/o
3 - overflow
    R1,D2(X2,B2)    

AH, Add Halfword
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The half word (2 bytes) located at the storage address specified by operand-2 (x2+b2+d2) is added to the register specified by operand-1 (r1). Operand-2 remains unchanged. The condition code is set as shown below.

   
 
     
     
     
     
     
     
x2=index
b2=base register
ddd2=displacement
 
   
4A RX BDDD
   
 
r1=register
 
 
 
     
     
     
 
  Condition Code
0 - op1=0, n/o
1 - op1<0, n/o
2 - op1>0, n/o
3 - overflow
    R1,D2(X2,B2)    

AL, Add Logical
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The full word (4 bytes) located at the storage address specified by operand-2 (x2+b2+d2) is added to the register specified by operand-1 (r1). Operand-2 remains unchanged. The condition code is set as shown below.

   
 
     
     
     
     
     
     
x2=index
b2=base register
ddd2=displacement
 
   
5E RX BDDD
   
 
r1=register
 
 
 
     
     
     
 
  Condition Code
0 - zero, no-carry
1 - not-zero, no-carry
2 - zero, carry
3 - not-zero, carry
    R1,D2(X2,B2)    

ALR, Add Logical Registers
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The register specified by operand-2 (r2) is added to the register specified by operand-1 (r1). Operand-2 remains unchanged. The condition code is set as shown below.

 
r1=register
 
 
 
         
         
         
r2=register
 
   
1E RR
  Condition Code
0 - zero, no-carry
1 - not-zero, no-carry
2 - zero, carry
3 - not-zero, carry
    R1,R2    

AP, Add Packed (Decimal)
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The data string located at the storage address specified by operand-2 (b2+d2) is added to the data string located at the storage address specified by operand-1 (b1+d1). Operand-2 remains unchanged. The operands may be different lengths with a maximum length of 16 bytes (or 31 digits since this is packed) for each operand. The condition code is set as shown below.

 
L2=length-1
 
 
 
     
     
     
 
     
     
     
b2=base register
ddd2=displacement
 
   
D5 LL BDDD BDDD
   
 
L1=length-1
 
 
 
     
     
     
     
 
   
 
b1=base register
ddd1=displacement
 
 
 
 
 
 
     
     
     
 
  Condition Code
0 - op1=0, n/o
1 - op1<0, n/o
2 - op1>0, n/o
3 - overflow
    D1(L1,B1),D2(L2,B2)    

AR, Add Registers
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The register specified by operand-2 (r2) is added to the register specified by operand-1 (r1). Operand-2 remains unchanged. The condition code is set as shown below.

 
r1=register
 
 
 
         
         
         
r2=register
 
   
1A RR
  Condition Code
0 - op1=0, n/o
1 - op1<0, n/o
2 - op1>0, n/o
3 - overflow
    R1,R2    

BAL, Branch and Link
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The next sequential address is placed in operand-1 (r1) as linkage information, a branch to operand-2 (x2+b2+d2) is performed.

   
 
     
     
     
     
     
     
x2=index
b2=base register
ddd2=displacement
 
   
45 RX BDDD
   
 
r1=register
 
 
 
     
     
     
 
   
    R1,D2(X2,B2)    

This instruction was originally intended for use with 24-bit addressing and is still provided for back-level compatibility. Only the rightmost 24 bits (bits 8-31) of the full word are used when branching or linking. The first 8 bits (bits 0-7) are not used as part of the address. Note: This instruction will work with 31-bit addressing mode but it is recommended that the BAS instruction be used instead of the BAL instruction.

BALR, Branch and Link Register
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The next sequential address is placed in operand-1 (r1) as linkage information, a branch to operand-2 (r2) is performed.

 
r1=register
 
 
 
         
         
         
r2=register
 
   
05 RR
  Note:
When the operand 2 value is zero, the link information is loaded without branching
    R1,R2    

This instruction was originally intended for use with 24-bit addressing and is still provided for back-level compatibility. Only the rightmost 24 bits (bits 8-31) of the full word are used when branching or linking. The first 8 bits (bits 0-7) are not used as part of the address.Note: This instruction will work with 31-bit addressing mode but it is recommended that the BASR instruction be used instead of the BALR instruction.

BAS, Branch and Save
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The next sequential address is placed in operand-1 (r1) as linkage information, a branch to operand-2 (x2+b2+d2) is performed.

   
 
     
     
     
     
     
     
x2=index
b2=base register
ddd2=displacement
 
   
4D RX BDDD
   
 
r1=register
 
 
 
     
     
     
 
   
    R1,D2(X2,B2)    

This instruction was introduced for use with 31-bit addressing and also works with 24-bit addressing mode. Only the rightmost 31 bits (bits 1-31) of the full word are used when branching or linking. The first bit (bit 0) is not used as part of the address.

BASR, Branch and Save Register
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The next sequential address is placed in operand-1 (r1) as linkage information, a branch to operand-2 (r2) is performed.

 
r1=register
 
 
 
         
         
         
r2=register
 
   
0D RR
  Note
When the operand 2 value is zero, the link information is loaded without branching
    R1,R2    

This instruction was introduced for use with 31-bit addressing and also works with 24-bit addressing mode. Only the rightmost 31 bits (bits 1-31) of the full word are used when branching or linking. The first bit (bit 0) is not used as part of the address.

BASSM, Branch and Save and Set Mode
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The next sequential address is placed in operand-1 (r1) as linkage information, a branch to operand-2 (r2) is performed. The addressing mode is also set by this instruction.

 
r1=register
 
 
 
         
         
         
r2=register
 
   
0C RR
   
    R1,R2    

BC, Branch on Condition
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If the condition-code (cc) has a "bit-ON" match with the instruction-mask (m1) then branch to the address specified by operand-2 (x2+b2+d2) else do the next sequential instruction.

   
 
     
     
     
     
     
     
x2=index
b2=base register
ddd2=displacement
 
   
47 MX BDDD
   
 
m1=mask
 
 
 
     
     
     
 
 
cc   relation mask Hex
0 - equal-zero 1000 X'8x'
1 - low-minus 0100 X'4x'
2 - high-plus 0010 X'2x'
3 - overflow 0001 X'1x'
    M1,D2(X2,B2)    

Branch on Condition Register
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If the condition-code (cc) has a "bit-ON" match with the instruction-mask (m1) then branch to the address specified by operand-2 (r2) else do the next sequential instruction.

 
m1=mask
 
 
 
         
         
         
r2=register
 
   
07 MR
   
    M1,R2  
cc   relation mask Hex
0 - equal-zero 1000 X'8x'
1 - low-minus 0100 X'4x'
2 - high-plus 0010 X'2x'
3 - overflow 0001 X'1x'

BCT, Branch on Count
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A one is subtracted from operand 1 (r1). If r1 decrements to zero then normal instruction sequencing proceeds else branch to address specified by operand 2.

   
 
     
     
     
     
     
     
x2=index
b2=base register
ddd2=displacement
 
   
46 RX BDDD
   
 
r1=register
 
 
 
     
     
     
 
   
    R1,D2(X2,B2)    

BCTR, Branch on Count Register
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A one is subtracted from operand 1 (r1). If r1 decrements to zero then normal instruction sequencing proceeds else branch to address specified by operand 2.

 
r1=register
 
 
 
         
         
         
r2=register
 
   
06 RR
  Note:
If r2 is zero then r1 is decremented but a branch is never taken.
    R1,R2    

BSM, Branch and Set Mode
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A branch is performed and the addressing mode is also set by this instruction.

 
r1=register
 
 
 
         
         
         
r2=register
 
   
0B RR
   
    R1,R2    

BXH, Branch on Index High
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Operand-1 (r1) is the index value that will be incremented. Operand-2 (b2+d2) is the address to branch to when the compare conditions are met. Operand-3 (r3) may be a single register or a register pair.

If operand-3 register number is even then a register pair are used as the increment and the compare value. If operand-3 is odd a single register is used as both the increment and the compare value. The increment is a signed binary number and may be used to increase or decrease the value in Operand-1

When the BXH instruction is executed the incrementing value specified by operand-3 is added to operand-1. Operand-1 is then compared with the compare value specified by operand-3 and if operand-1 is high then a branch is performed. Otherwise, the next sequential instruction is executed.

 
r1=register
 
 
 
     
     
     
     
     
     
b2=base register
ddd2=displacement
 
   
86 RR BDDD
   
 
r3=register-pair
 
 
 
     
     
     
 
   
    R1,R3,D2(B2)    

BXLE, Branch on Index Low or Equal
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Operand-1 (r1) is the index value that will be incremented. Operand-2 (b2+d2) is the address to branch to when the compare conditions are met. Operand-3 (r3) may be a single register or a register pair.

If operand-3 register number is even then a register pair are used as the increment and the compare value. If operand-3 is odd a single register is used as both the increment and the compare value. The increment is a signed binary number and may be used to increase or decrease the value in Operand-1

When the BXLE instruction is executed the incrementing value specified by operand-3 is added to operand-1. Operand-1 is then compared with the compare value specified by operand-3 and if operand-1 is low or equal then a branch is performed. Otherwise, the next sequential instruction is executed.

 
r1=register
 
 
 
     
     
     
     
     
     
b2=base register
ddd2=displacement
 
   
87 RR BDDD
   
 
r3=register-pair
 
 
 
     
     
     
 
   
    R1,R3,D2(B2)    

C, Compare
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Operand-1 (r1) is compared with the data string located at the storage address specifed by operand-2 (x2+b2+d2) . The result is posted in the condition code.

   
 
     
     
     
     
     
     
x2=index
b2=base register
ddd2=displacement
 
   
59 RX BDDD
   
 
r1=register
 
 
 
     
     
     
 
  Condition Code
0 - equal
1 - op1-low
2 - op1-high
3 - --
    R1,D2(X2,B2)    

CDS, Compare Double and Swap
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Operand-1 (r1) and operand-2 (b2+d2) are compared. If equal then operand-3 (r3) is stored at the storage address specified by operand-2 (b2+d2). Otherwise, the data string located at the address specified by operand-2 (b2+d2) is loaded into operand-1 (r1). The operands are 64 bits.

 
r1=register-pair
 
 
 
     
     
     
     
     
     
b2=base register
ddd2=displacement
 
   
BB RR BDDD
   
 
r3=register-pair
 
 
 
     
     
     
 
   
    R1,R3,D2(B2)    

CH, Compare Halfword
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Operand-1 (r1) is compared with the data string located at the storage address specifed by operand-2 (x2+b2+d2). The result is posted in the condition code.

   
 
     
     
     
     
     
     
x2=index
b2=base register
ddd2=displacement
 
   
49 RX BDDD
   
 
r1=register
 
 
 
     
     
     
 
  Condition Code
0 - equal
1 - op1-low
2 - op1-high
3 - --
    R1,D2(X2,B2)    

CL, Compare Logical
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Operand-1 (r1) is compared with the data string located at the storage address specified by operand-2 (x2+b2+d2). The result is posted in the condition code. This is a full word (32-bit) comparison.

   
 
     
     
     
     
     
     
x2=index
b2=base register
ddd2=displacement
 
   
55 RX BDDD
   
 
r1=register
 
 
 
     
     
     
 
  Condition Code
0 - equal
1 - op1-low
2 - op1-high
3 - --
    R1,D2(X2,B2)    

CLC, Compare Logical Characters
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The data string located at the storage address specified by operand-2 (b2+d2) is compared to the data string located at the storage address specified by operand-1 (b1+d1). Both operands remains unchanged. The number of bytes compared is determined by the length specified in the 2nd byte of the CLC instruction. The length specified is actually the length-1 or x'00' through x'FF'. The length of each operand is the same. For example, if x'FF' is specified as the length then operand-1 would be 256 bytes and operand-2 would be 256 bytes. The condition code is set as shown below.

 
LL=length-1
value x'00' to x'FF'
 
 
 
     
     
     
 
     
     
     
b2=base register
ddd2=displacement
 
   
D5 LL BDDD BDDD
   
 
b1=base register
ddd1=displacement
 
 
 
 
 
 
     
     
     
 
  Condition Code
0 - equal
1 - op1-low
2 - op1-high
3 - --
    D1(L,B1),D2(B2)    

CLCL, Compare Logical Characters Long
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The data string identified by operand-1 is compared with the data string identified by operand-2. Both operands are register-pairs. The first register of each operand needs to be loaded with the storage addresses of the data strings to be compared. The second register of each operands needs to be loaded with the length of each operand. The data strings may be different length. The high-order byte of the second register of operand-2 is treated as the padding character if the operands are different lengths. The compare proceeds from left to right, low storage to high storage and as each character is found to be equal the length registers are decremented. If the CLCL results in and equal condition then the length registers should be zero with one exception. Remember, if a pad character was specified in the high-order (bits 0-7) byte of the second register of operand-2 then only the remaining three bytes (bits 8-31) will be zero. The results are posted in the condition code.

 
r1=register-pair
 
 
 
         
         
         
r2=register-pair
 
   
0F RR
  Condition Code
0 - equal
1 - op1-low
2 - op1-high
3 - --
    R1,R2    

CLI, Compare Logical Immediate
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Operand-2 (the immediate data that is the second byte of the instruction itself) is compared to the one-byte at the storage address specifed by operand-1 (b1+d1). The results of the compare are posted in the condition code

 
I2=immediate
 
 
 
     
     
     
     
     
     
b1=base register
ddd1=displacement
 
   
95 ii BDDD
  Condition Code
0 - equal
1 - op1-low
2 - op1-high
3 - --
    D1(B1),I2    

CLM, Compare Logical under Mask
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Operand-1 (r1) under control of the mask (m3) is compared to the data string located at the storage location specified by operand-2. The results are posted in the condition code.

 
r1=register
 
 
 
     
     
     
     
     
     
b2=base register
ddd2=displacement
 
   
BD RM BDDD
   
 
m3=mask
 
 
 
     
     
     
 
  Condition Code
0 - equal
or mask-bits all zero
1 - op1-low
2 - op1-high
3 - --
    R1,M3,D2(B2)    

CLR, Compare Logical Registers
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Operand-1 (r1) is compared with operand-2 (r2). The compare is a logical compare of all 32-bits. The results are posted in the condition code.

 
r1=register
 
 
 
         
         
         
r2=register
 
   
15 RR
  Condition Code
0 - equal
1 - op1-low
2 - op1-high
3 - --
    R1,R2    

CP, Compare Packed (Decimal)
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The data string located at the storage address specified by operand-2 (b2+d2) is compared to the data string located at the storage address specified by operand-1 (b1+d1). The operands may be different lengths with a maximum length of 16 bytes (or 31 digits since this is packed) for each operand. This is an arithmetic comparison. The condition code is set as shown below.

 
L2=length-1
 
 
 
     
     
     
 
     
     
     
b2=base register
ddd2=displacement
 
   
F9 LL BDDD BDDD
   
 
L1=length-1
 
 
 
     
     
     
     
 
   
 
b1=base register
ddd1=displacement
 
 
 
 
 
 
     
     
     
 
  Condition Code
0 - equal
1 - op1<op2
2 - op1>op2
3 - --
    D1(L1,B1),D2(L2,B2)    

CR, Compare Registers
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The register specified by operand-2 (r2) is compared to the the register specified by operand-1 (r1). Operand-2 remains unchanged. The condition code is set as shown below.

 
r1=register
 
 
 
         
         
         
r2=register
 
   
19 RR
  Condition Code
0 - equal
1 - op1<op2
2 - op1>op2
3 - --
    R1,R2    

CS, Compare and Swap
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Operand-1 (r1) and operand-2 (b2+d2) are compared. If equal then operand-3 (r3) is stored at the storage address specified by operand-2 (b2+d2). Otherwise, the data string located at the address specified by operand-2 (b2+d2) is loaded into operand-1 (r1). The operands are 32 bits.

 
r1=register
 
 
 
     
     
     
     
     
     
b2=base register
ddd2=displacement
 
   
BA RR BDDD
   
 
r3=register
 
 
 
     
     
     
 
   
    R1,R3,D2(B2)    

CVB, Convert to Binary
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The data string at the storage location specified by operand-2 (x2+b2+d2) is translated from decimal to binary and the result is stored in operand-1 (r1). Operand-2 remains unchanged and should be an 8-byte packed (15 digit and sign), decimal value

   
 
     
     
     
     
     
     
x2=index
b2=base register
ddd2=displacement
 
   
4F RX BDDD
   
 
r1=register
 
 
 
     
     
     
 
   
    R1,D2(X2,B2)    

CVD, Convert to Decimal
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Operand-1 (r1) is translated from binary to decimal and the result is stored at the storage location specified by operand-2 (x2+b2+d2). Operand-1 remains unchanged. Operand-2 should be an 8-byte packed (15 digit and sign), decimal value

   
 
     
     
     
     
     
     
x2=index
b2=base register
ddd2=displacement
 
   
4E RX BDDD
   
 
r1=register
 
 
 
     
     
     
 
   
    R1,D2(X2,B2)    

D, Divide
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Operand-1 (r1) is an even/odd pair of registers (dividend) that is divided by the value at the storage location specified by operand-2 (x2+b2+d2). The remainder is put in r1-even and the quotient is put in r1-odd.

   
 
     
     
     
     
     
     
x2=index
b2=base register
ddd2=displacement
 
   
5D RX BDDD
   
 
r1=even/odd pair
 
 
 
     
     
     
 
   
    R1,D2(X2,B2)    

DP, Divide Packed (Decimal)
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The data string located at the storage address specified by operand-1 (b1+d1) is divided by the data string located at the storage address specified by operand-2 (b2+d2). Operand-2 remains unchanged.

 
L2=length-1
 
 
 
     
     
     
 
     
     
     
b2=base register
ddd2=displacement
 
   
FD LL BDDD BDDD
   
 
L1=length-1
 
 
 
     
     
     
     
 
   
 
b1=base register
ddd1=displacement
 
 
 
 
 
 
     
     
     
 
   
    D1(L1,B1),D2(L2,B2)    

DR, Divide Registers
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Operand-1 (r1) is an even/odd pair of registers (dividend) that is divided by operand-2 (r2). The remainder is put in r1-even and the quotient is put in r1-odd.

 
r1=register
 
 
 
         
         
         
r2=register
 
   
1D RR
   
    R1,R2    

ED, Edit
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The data string located at the storage address specified by operand-2 (b2+d2) is integrated with the data string at the storage address specified by operand-1. Operand-2 (b2+d2) remains unchanged. Operand-1 should be initialized with an edit word. The length is determined by the length specified in the 2nd byte of the Edit instruction.

 
LL=length-1
value x'00' to x'FF'
 
 
 
     
     
     
 
     
     
     
b2=base register
ddd2=displacement
 
   
DE LL BDDD BDDD
   
 
b1=base register
ddd1=displacement
 
 
 
 
 
 
     
     
     
 
   
    D1(L,B1),D2(B2)    

EDMK, Edit and Mark
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The data string located at the storage address specified by operand-2 (b2+d2) is integrated with the data string at the storage address specified by operand-1. Operand-2 (b2+d2) remains unchanged. Operand-1 should be initialized with an edit word. The length is determined by the length specified in the 2nd byte of the EDMK instruction.The address of the first significant byte is put in general register 1.

 
LL=length-1
value x'00' to x'FF'
 
 
 
     
     
     
 
     
     
     
b2=base register
ddd2=displacement
 
   
DF LL BDDD BDDD
   
 
b1=base register
ddd1=displacement
 
 
 
 
 
 
     
     
     
 
   
    D1(L,B1),D2(B2)    

EX, Execute
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The instruction at the address specified by operand-2 (x2+b2+d2) is modified then executed using the contents of operand-1 (r1). Bits 8-15 of operand-1 and bits 24-31 of operand-1 are OR'ed together.

   
 
     
     
     
     
     
     
x2=index
b2=base register
ddd2=displacement
 
   
44 RX BDDD
   
 
r1=register
 
 
 
     
     
     
 
   
    R1,D2(X2,B2)    

IC, Insert Character
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The byte at the address specified by operand-2 (x2+b2+d2) is inserted into bit positions 24-31 operand-1 (r1).

   
 
     
     
     
     
     
     
x2=index
b2=base register
ddd2=displacement
 
   
43 RX BDDD
   
 
r1=register
 
 
 
     
     
     
 
   
    R1,D2(X2,B2)    

ICM, Insert Characters under Mask
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Bytes from storage location specified by operand-2 (b2+d2) are inserted into operand-1 (r1) under control of the mask (m3)

 
r1=register
 
 
 
     
     
     
     
     
     
b2=base register
ddd2=displacement
 
   
BF RM BDDD
   
 
m3=mask
 
 
 
     
     
     
 
   
    R1,M3,D2(B2)    

L, Load
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The four bytes at the storage address specified by operand-2 (x2+b2+d2) is loaded into the register specified by operand-1 (r1).

   
 
     
     
     
     
     
     
x2=index
b2=base register
ddd2=displacement
 
   
58 RX BDDD
   
 
r1=register
 
 
 
     
     
     
 
   
    R1,D2(X2,B2)    

LA, Load Address
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The actual value of operand-2 (x2+b2+d2) is loaded into the register specified by operand-1 (r1).

   
 
     
     
     
     
     
     
x2=index
b2=base register
ddd2=displacement
 
   
41 RX BDDD
   
 
r1=register
 
 
 
     
     
     
 
   
    R1,D2(X2,B2)    

LCR, Load Complement Registers
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The two's complement of operand-2 (r2) is put into operand-1 (r1). For example, if the register specified by operand-2 contained x'00000010' then after the LCR instruction was executed the register specified by operand-1 would contain x'FFFFFFF0'.

 
r1=register
 
 
 
         
         
         
r2=register
 
   
13 RR
   
    R1,R2    

LH, Load Halfword
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The two bytes (halfword) located at the storage address specified by operand-2 (x2+b2+d2) is loaded into the rightmost two bytes (bits 16-31) of the register specified by operand-1 (r1).

   
 
     
     
     
     
     
     
x2=index
b2=base register
ddd2=displacement
 
   
48 RX BDDD
   
 
r1=register
 
 
 
     
     
     
 
   
    R1,D2(X2,B2)    

LM, Load Multiples
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The set of registers starting with operand-1 (r1) and ending with (r3) are loaded from the storage location specified by operand-2 (b2+d2).

 
r1=register
 
 
 
     
     
     
     
     
     
b2=base register
ddd2=displacement
 
   
98 RR BDDD
   
 
r3=register
 
 
 
     
     
     
 
   
    R1,R3,D2(B2)    

LNR, Load Negative Registers
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The two's complement of the absolute value of operand-2 (r2) is put into operand-1 (r1).

 
r1=register
 
 
 
         
         
         
r2=register
 
   
11 RR
   
    R1,R2    

LPR, Load Positive Registers
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The absolute value of operand-2 (r2) is put into operand-1 (r1).

 
r1=register
 
 
 
         
         
         
r2=register
 
   
10 RR
   
    R1,R2    

LR, Load Register
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The value of operand-2 (r2) is put into operand-1 (r1).

 
r1=register
 
 
 
         
         
         
r2=register
 
   
18 RR
   
    R1,R2    

LTR, Load and Test Register
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Operand-2 (r2) is put into operand-1 (r1). The sign and magnitude of operand-2 (r2), treated as a 32-bit signed binary integer are indicated in the condition code.

 
r1=register
 
 
 
         
         
         
r2=register
 
   
12 RR
   
    R1,R2   Condition Code
0 - result=zero
1 - result<zero
2 - result>zero
3 - --

M, Multiply
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The value located at the storage address specified by operand-2 (x2+b2+d2) is multiplied with the 2nd-word (i.e. the second register of the pair) of operand-1 (r1). The doubleword product is put in operand-1.

   
 
     
     
     
     
     
     
x2=index
b2=base register
ddd2=displacement
 
   
5C RX BDDD
   
 
r1=even/odd-pair
 
 
 
     
     
     
 
   
    R1,D2(X2,B2)    

MH, Multiply Halfword
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The value located at the storage address specified by operand-2 (x2+b2+d2) is multiplied with operand-1 (r1). The product is put in operand-1.

   
 
     
     
     
     
     
     
x2=index
b2=base register
ddd2=displacement
 
   
4C RX BDDD
   
 
r1=register
 
 
 
     
     
     
 
   
    R1,D2(X2,B2)    

MP, Multiply Packed (Decimal)
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The product of the data string located at the storage address specified by operand-2 (b2+d2) and the data string located at the storage address specified by operand-1 (b1+d1) is placed in the operand-1 location. Operand-2 remains unchanged. The operands may be different lengths with a maximum length of 16 bytes (or 31 digits since this is packed) for each operand. The condition code is set as shown below.

 
L2=length-1
 
 
 
     
     
     
 
     
     
     
b2=base register
ddd2=displacement
 
   
FC LL BDDD BDDD
   
 
L1=length-1
 
 
 
     
     
     
     
 
   
 
b1=base register
ddd1=displacement
 
 
 
 
 
 
     
     
     
 
  Condition Code
0 - op1=0, n/o
1 - op1<0, n/o
2 - op1>0, n/o
3 - overflow
    D1(L1,B1),D2(L2,B2)    

MR, Multiply Registers
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The second word (odd-register) of operand-1 (r1) is multiplied by operand-2 (r2), the doubleword product is put in operand-1 (r1, even/odd-pair).

 
r1=even/odd-pair
 
 
 
         
         
         
r2=register
 
   
1C RR
   
    R1,R2    

MVC, Move Characters
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The data string located at the storage address specified by operand-2 (b2+d2) is moved to the storage address specified by operand-1 (b1+d1). Operand-2 remains unchanged. The number of bytes moved is determined by the length specified in the 2nd byte of the MVC instruction.

 
LL=length-1
value x'00' to x'FF'
 
 
 
     
     
     
 
     
     
     
b2=base register
ddd2=displacement
 
   
D2 LL BDDD BDDD
   
 
b1=base register
ddd1=displacement
 
 
 
 
 
 
     
     
     
 
   
    D1(L,B1),D2(B2)    

MVCIN, Move Characters Inverse
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The data string located at the storage address specified by operand-2 (b2+d2) is moved to the storage address specified by operand-1 (b1+d1) with the left-to-right sequence of the bytes inverted. Operand-2 remains unchanged. The number of bytes moved is determined by the length specified in the 2nd byte of the MVC instruction.

 
LL=length-1
value x'00' to x'FF'
 
 
 
     
     
     
 
     
     
     
b2=base register
ddd2=displacement
 
   
E8 LL BDDD BDDD
   
 
b1=base register
ddd1=displacement
 
 
 
 
 
 
     
     
     
 
   
    D1(L,B1),D2(B2)    

MVCL, Move Characters Long
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The data string identified by operand-2 (r2) is moved to the storage location identified by operand-1 (r1). Both operands are register-pairs. The first register of each operand needs to be loaded with the storage addresses of the data strings. The second register of each operands needs to be loaded with the length of each operand. The data strings may be different length. The high-order byte of the second register of operand-2 is treated as the padding character if the operands or different lengths. The move proceeds from left to right, low storage to high storage and as each character is moved the length registers are decremented.

 
r1=register-Pair
 
 
 
         
         
         
r2=register-Pair
 
   
0E RR
   
    R1,R2    

MVI, Move Immediate
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Operand-2 (the immediate data that is the second byte of the instruction itself) is moved to the storage address specifed by operand-1 (b1+d1).

 
I2=immediate
 
 
 
     
     
     
     
     
     
b1=base register
ddd1=displacement
 
   
92 ii BDDD
   
    D1(B1),I2    

MVN, Move Numerics
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The rightmost 4-bits of each byte of the data string located at the storage address specified by operand-2 (b2+d2) are put into the storage address specified by operand-1 (b1+d1). Operand-2 remains unchanged. The length is determined by the value in the 2nd byte of the MVN instruction.

 
LL=length-1
value x'00' to x'FF'
 
 
 
     
     
     
 
     
     
     
b2=base register
ddd2=displacement
 
   
D1 LL BDDD BDDD
   
 
b1=base register
ddd1=displacement
 
 
 
 
 
 
     
     
     
 
   
    D1(L,B1),D2(B2)    

MVO, Move with Offset
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The data string located at the storage address specified by operand-2 (b2+d2) is shifted left four bits and put into the storage address specified by operand-1 (b1+d1). The rightmost 4-bits of operand-1 remain unchanged.

 
L2=length-1
 
 
 
     
     
     
 
     
     
     
b2=base register
ddd2=displacement
 
   
F1 LL BDDD BDDD
   
 
L1=length-1
 
 
 
     
     
     
     
 
   
 
b1=base register
ddd1=displacement
 
 
 
 
 
 
     
     
     
 
   
    D1(L1,B1),D2(L2,B2)    

MVZ, Move Zones
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The lefmost 4-bits of each byte of the data string located at the storage address specified by operand-2 (b2+d2) are put into the storage address specified by operand-1 (b1+d1). Operand-2 remains unchanged. The length is determined by the value in the 2nd byte of the MVZ instruction.

 
LL=length-1
value x'00' to x'FF'
 
 
 
     
     
     
 
     
     
     
b2=base register
ddd2=displacement
 
   
D3 LL BDDD BDDD
   
 
b1=base register
ddd1=displacement
 
 
 
 
 
 
     
     
     
 
   
    D1(L,B1),D2(B2)    

N, And
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The content of operand-1 (r1) is AND'ed with the data string located at the storage address specified by operand-2 (x2+b2+d2). The results of the AND'ing process is put into operand-1.

   
 
     
     
     
     
     
     
x2=index
b2=base register
ddd2=displacement
 
   
54 RX BDDD
   
 
r1=register
 
 
 
     
     
     
 
  Condition Code
0 - result-is-zero
1 - result-not-zero
2 - --
3 - --

    R1,D2(X2,B2)    

NC, And Characters
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The data string located at the storage address specified by operand-1 (b1+d1) is AND'ed with the data string located at the storage address specified by operand-2 (b2+d2). The results of the AND'ing process is put into operand-1.

 
LL=length-1
value x'00' to x'FF'
 
 
 
     
     
     
 
     
     
     
b2=base register
ddd2=displacement
 
   
D4 LL BDDD BDDD
   
 
b1=base register
ddd1=displacement
 
 
 
 
 
 
     
     
     
 
  Condition Code
0 - result-is-zero
1 - result-not-zero
2 - --
3 - --
    D1(L,B1),D2(B2)    

NI, And Immediate
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The data string located at the storage address specified by operand-1 (b1+d1) is AND'ed with operand-2 (i2 is immediate data included as the second byte of the instruction itself). The results of the AND'ing process is put into operand-1.

 
i2=immediate
 
 
 
     
     
     
     
     
     
b1=base register
ddd1=displacement
 
   
94 ii BDDD
   
    D1(B1),I2   Condition Code
0 - result-is-zero
1 - result-not-zero
2 - --
3 - --

NR, And Registers
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The content of operand-1 (r1) is AND'ed with the content of operand-2 (r2). The results of the AND'ing process is put into operand-1.

 
r1=register