370 Instructions  Problem-State http://www.simotime.com  Copyright © 1987-2010 SimoTime Enterprises All Rights Reserved

Introduction
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This document is intended to be used as a quick reference for the mainframe, problem-state, non-floating point instructions. The source code for the sample program that executes each of the problem-state, non-floating point instructions provides additional detail.

Instruction List sequenced by Mnemonic Opcode
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The following list is sequenced by the Mnemonic Opcode.

Instruction List sequenced by Hexadecimal Opcode
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The following list is sequenced by the Hexadecimal Opcode.

Instruction Overview
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This program may serve as a tutorial for programmers that are new to 370 assembler or as a reference for experienced programmers.

A, Add
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The full word (4 bytes) located at the storage address specified by operand-2 (x2+b2+d2} is added to the register specified by operand-1(r1). Operand-2 remains unchanged. The condition code is set as shown below.

AH, Add Halfword
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The half word (2 bytes) located at the storage address specified by operand-2 (x2+b2+d2) is added to the register specified by operand-1 (r1). Operand-2 remains unchanged. The condition code is set as shown below.

AL, Add Logical
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The full word (4 bytes) located at the storage address specified by operand-2 (x2+b2+d2) is added to the register specified by operand-1 (r1). Operand-2 remains unchanged. The condition code is set as shown below.

ALR, Add Logical Registers
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The register specified by operand-2 (r2) is added to the register specified by operand-1 (r1). Operand-2 remains unchanged. The condition code is set as shown below.

AP, Add Packed (Decimal)
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The data string located at the storage address specified by operand-2 (b2+d2) is added to the data string located at the storage address specified by operand-1 (b1+d1). Operand-2 remains unchanged. The operands may be different lengths with a maximum length of 16 bytes (or 31 digits since this is packed) for each operand. The condition code is set as shown below.

AR, Add Registers
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The register specified by operand-2 (r2) is added to the register specified by operand-1 (r1). Operand-2 remains unchanged. The condition code is set as shown below.

BAL, Branch and Link
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The next sequential address is placed in operand-1 (r1) as linkage information, a branch to operand-2 (x2+b2+d2) is performed.

This instruction was originally intended for use with 24-bit addressing and is still provided for back-level compatibility. Only the rightmost 24 bits (bits 8-31) of the full word are used when branching or linking. The first 8 bits (bits 0-7) are not used as part of the address. Note: This instruction will work with 31-bit addressing mode but it is recommended that the BAS instruction be used instead of the BAL instruction.

BALR, Branch and Link Register
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The next sequential address is placed in operand-1 (r1) as linkage information, a branch to operand-2 (r2) is performed.

This instruction was originally intended for use with 24-bit addressing and is still provided for back-level compatibility. Only the rightmost 24 bits (bits 8-31) of the full word are used when branching or linking. The first 8 bits (bits 0-7) are not used as part of the address.Note: This instruction will work with 31-bit addressing mode but it is recommended that the BASR instruction be used instead of the BALR instruction.

BAS, Branch and Save
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The next sequential address is placed in operand-1 (r1) as linkage information, a branch to operand-2 (x2+b2+d2) is performed.

This instruction was introduced for use with 31-bit addressing and also works with 24-bit addressing mode. Only the rightmost 31 bits (bits 1-31) of the full word are used when branching or linking. The first bit (bit 0) is not used as part of the address.

BASR, Branch and Save Register
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The next sequential address is placed in operand-1 (r1) as linkage information, a branch to operand-2 (r2) is performed.

This instruction was introduced for use with 31-bit addressing and also works with 24-bit addressing mode. Only the rightmost 31 bits (bits 1-31) of the full word are used when branching or linking. The first bit (bit 0) is not used as part of the address.

BASSM, Branch and Save and Set Mode
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The next sequential address is placed in operand-1 (r1) as linkage information, a branch to operand-2 (r2) is performed. The addressing mode is also set by this instruction.

BC, Branch on Condition
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If the condition-code (cc) has a "bit-ON" match with the instruction-mask (m1) then branch to the address specified by operand-2 (x2+b2+d2) else do the next sequential instruction.

Branch on Condition Register
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If the condition-code (cc) has a "bit-ON" match with the instruction-mask (m1) then branch to the address specified by operand-2 (r2) else do the next sequential instruction.

BCT, Branch on Count
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A one is subtracted from operand 1 (r1). If r1 decrements to zero then normal instruction sequencing proceeds else branch to address specified by operand 2.

BCTR, Branch on Count Register
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A one is subtracted from operand 1 (r1). If r1 decrements to zero then normal instruction sequencing proceeds else branch to address specified by operand 2.

BSM, Branch and Set Mode
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A branch is performed and the addressing mode is also set by this instruction.

BXH, Branch on Index High
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Operand-1 (r1) is the index value that will be incremented. Operand-2 (b2+d2) is the address to branch to when the compare conditions are met. Operand-3 (r3) may be a single register or a register pair.

If operand-3 register number is even then a register pair are used as the increment and the compare value. If operand-3 is odd a single register is used as both the increment and the compare value. The increment is a signed binary number and may be used to increase or decrease the value in Operand-1

When the BXH instruction is executed the incrementing value specified by operand-3 is added to operand-1. Operand-1 is then compared with the compare value specified by operand-3 and if operand-1 is high then a branch is performed. Otherwise, the next sequential instruction is executed.

BXLE, Branch on Index Low or Equal
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Operand-1 (r1) is the index value that will be incremented. Operand-2 (b2+d2) is the address to branch to when the compare conditions are met. Operand-3 (r3) may be a single register or a register pair.

If operand-3 register number is even then a register pair are used as the increment and the compare value. If operand-3 is odd a single register is used as both the increment and the compare value. The increment is a signed binary number and may be used to increase or decrease the value in Operand-1

When the BXLE instruction is executed the incrementing value specified by operand-3 is added to operand-1. Operand-1 is then compared with the compare value specified by operand-3 and if operand-1 is low or equal then a branch is performed. Otherwise, the next sequential instruction is executed.

C, Compare
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Operand-1 (r1) is compared with the data string located at the storage address specifed by operand-2 (x2+b2+d2) . The result is posted in the condition code.

CDS, Compare Double and Swap
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Operand-1 (r1) and operand-2 (b2+d2) are compared. If equal then operand-3 (r3) is stored at the storage address specified by operand-2 (b2+d2). Otherwise, the data string located at the address specified by operand-2 (b2+d2) is loaded into operand-1 (r1). The operands are 64 bits.

CH, Compare Halfword
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Operand-1 (r1) is compared with the data string located at the storage address specifed by operand-2 (x2+b2+d2). The result is posted in the condition code.

CL, Compare Logical
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Operand-1 (r1) is compared with the data string located at the storage address specified by operand-2 (x2+b2+d2). The result is posted in the condition code. This is a full word (32-bit) comparison.

CLC, Compare Logical Characters
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The data string located at the storage address specified by operand-2 (b2+d2) is compared to the data string located at the storage address specified by operand-1 (b1+d1). Both operands remains unchanged. The number of bytes compared is determined by the length specified in the 2nd byte of the CLC instruction. The length specified is actually the length-1 or x'00' through x'FF'. The length of each operand is the same. For example, if x'FF' is specified as the length then operand-1 would be 256 bytes and operand-2 would be 256 bytes. The condition code is set as shown below.

CLCL, Compare Logical Characters Long
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The data string identified by operand-1 is compared with the data string identified by operand-2. Both operands are register-pairs. The first register of each operand needs to be loaded with the storage addresses of the data strings to be compared. The second register of each operands needs to be loaded with the length of each operand. The data strings may be different length. The high-order byte of the second register of operand-2 is treated as the padding character if the operands are different lengths. The compare proceeds from left to right, low storage to high storage and as each character is found to be equal the length registers are decremented. If the CLCL results in and equal condition then the length registers should be zero with one exception. Remember, if a pad character was specified in the high-order (bits 0-7) byte of the second register of operand-2 then only the remaining three bytes (bits 8-31) will be zero. The results are posted in the condition code.

CLI, Compare Logical Immediate
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Operand-2 (the immediate data that is the second byte of the instruction itself) is compared to the one-byte at the storage address specifed by operand-1 (b1+d1). The results of the compare are posted in the condition code

CLM, Compare Logical under Mask
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Operand-1 (r1) under control of the mask (m3) is compared to the data string located at the storage location specified by operand-2. The results are posted in the condition code.

CLR, Compare Logical Registers
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Operand-1 (r1) is compared with operand-2 (r2). The compare is a logical compare of all 32-bits. The results are posted in the condition code.

CP, Compare Packed (Decimal)
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The data string located at the storage address specified by operand-2 (b2+d2) is compared to the data string located at the storage address specified by operand-1 (b1+d1). The operands may be different lengths with a maximum length of 16 bytes (or 31 digits since this is packed) for each operand. This is an arithmetic comparison. The condition code is set as shown below.

CR, Compare Registers
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The register specified by operand-2 (r2) is compared to the the register specified by operand-1 (r1). Operand-2 remains unchanged. The condition code is set as shown below.

CS, Compare and Swap
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Operand-1 (r1) and operand-2 (b2+d2) are compared. If equal then operand-3 (r3) is stored at the storage address specified by operand-2 (b2+d2). Otherwise, the data string located at the address specified by operand-2 (b2+d2) is loaded into operand-1 (r1). The operands are 32 bits.

CVB, Convert to Binary
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The data string at the storage location specified by operand-2 (x2+b2+d2) is translated from decimal to binary and the result is stored in operand-1 (r1). Operand-2 remains unchanged and should be an 8-byte packed (15 digit and sign), decimal value

CVD, Convert to Decimal
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Operand-1 (r1) is translated from binary to decimal and the result is stored at the storage location specified by operand-2 (x2+b2+d2). Operand-1 remains unchanged. Operand-2 should be an 8-byte packed (15 digit and sign), decimal value

D, Divide
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Operand-1 (r1) is an even/odd pair of registers (dividend) that is divided by the value at the storage location specified by operand-2 (x2+b2+d2). The remainder is put in r1-even and the quotient is put in r1-odd.

DP, Divide Packed (Decimal)
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The data string located at the storage address specified by operand-1 (b1+d1) is divided by the data string located at the storage address specified by operand-2 (b2+d2). Operand-2 remains unchanged.

DR, Divide Registers
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Operand-1 (r1) is an even/odd pair of registers (dividend) that is divided by operand-2 (r2). The remainder is put in r1-even and the quotient is put in r1-odd.

ED, Edit
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The data string located at the storage address specified by operand-2 (b2+d2) is integrated with the data string at the storage address specified by operand-1. Operand-2 (b2+d2) remains unchanged. Operand-1 should be initialized with an edit word. The length is determined by the length specified in the 2nd byte of the Edit instruction.

EDMK, Edit and Mark
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The data string located at the storage address specified by operand-2 (b2+d2) is integrated with the data string at the storage address specified by operand-1. Operand-2 (b2+d2) remains unchanged. Operand-1 should be initialized with an edit word. The length is determined by the length specified in the 2nd byte of the EDMK instruction.The address of the first significant byte is put in general register 1.

EX, Execute
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The instruction at the address specified by operand-2 (x2+b2+d2) is modified then executed using the contents of operand-1 (r1). Bits 8-15 of operand-1 and bits 24-31 of operand-1 are OR'ed together.

IC, Insert Character
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The byte at the address specified by operand-2 (x2+b2+d2) is inserted into bit positions 24-31 operand-1 (r1).

ICM, Insert Characters under Mask
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Bytes from storage location specified by operand-2 (b2+d2) are inserted into operand-1 (r1) under control of the mask (m3)

L, Load
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The four bytes at the storage address specified by operand-2 (x2+b2+d2) is loaded into the register specified by operand-1 (r1).

LA, Load Address
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The actual value of operand-2 (x2+b2+d2) is loaded into the register specified by operand-1 (r1).

LCR, Load Complement Registers
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The two's complement of operand-2 (r2) is put into operand-1 (r1). For example, if the register specified by operand-2 contained x'00000010' then after the LCR instruction was executed the register specified by operand-1 would contain x'FFFFFFF0'.

LH, Load Halfword
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The two bytes (halfword) located at the storage address specified by operand-2 (x2+b2+d2) is loaded into the rightmost two bytes (bits 16-31) of the register specified by operand-1 (r1).

LM, Load Multiples
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The set of registers starting with operand-1 (r1) and ending with (r3) are loaded from the storage location specified by operand-2 (b2+d2).

LNR, Load Negative Registers
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The two's complement of the absolute value of operand-2 (r2) is put into operand-1 (r1).

LPR, Load Positive Registers
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The absolute value of operand-2 (r2) is put into operand-1 (r1).

LR, Load Register
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The value of operand-2 (r2) is put into operand-1 (r1).