| When
technology complements business |
Problem-State |
|
|
|
This document is intended to be used as a quick reference for the
mainframe, problem-state, non-floating point instructions. The source code for
the
sample program that executes each of the
problem-state, non-floating point instructions provides additional
detail.
The following list is sequenced by the Mnemonic Opcode.
| |
Instruction |
Mnemonic |
Hex |
Format |
| |
Add |
A |
5A |
R1,D2(X2,B2) |
| |
Add
Halfword |
AH |
4A |
R1,D2(X2,B2) |
| |
Add
Logical |
AL |
5E |
R1,D2(X2,B2) |
| |
Add Logical
Registers |
ALR |
1E |
R1,R2 |
| |
Add Packed
(Decimal) |
AP |
FA |
D1(L1,B1),D2(L2,B2) |
| |
Add
Registers |
AR |
1A |
R1,R2 |
| |
Branch and
Link |
BAL |
45 |
R1,D2(X2,B2) |
| |
Branch and Link
Register |
BALR |
05 |
R1,R2 |
| |
Branch and
Save |
BAS |
4D |
R1,D2(X2,B2) |
| |
Branch and Save
Register |
BASM |
0D |
R1,R2 |
| |
Branch, Save and
Set Mode |
BASSM |
0C |
R1,R2 |
| |
Branch on
Condition |
BC |
47 |
M1,D2(X2,B2) |
| |
Branch on Condition
Register |
BCR |
07 |
M1,R2 |
| |
Branch on
Count |
BCT |
46 |
R1,D2((X2,B2) |
| |
Branch on Count
Register |
BCTR |
06 |
R1,R2 |
| |
Branch and Set
Mode |
BSM |
0B |
R1,R2 |
| |
Branch on Index
High |
BXH |
86 |
R1,R3,D2(B2) |
| |
Branch on Index
Low/Equal |
BXLE |
87 |
R1,R3,D2(B2) |
| |
Compare |
C |
59 |
R1,D2(X2,B2) |
| |
Compare Double and
Swap |
CDS |
BB |
R1,R3,D29B2) |
| |
Compare
Halfword |
CH |
49 |
R1,D2(X2,B2) |
| |
Compare
Logical |
CL |
55 |
R1,D2(X2,B2) |
| |
Compare Logical
Characters |
CLC |
D5 |
D1(L,B1),D2(B2) |
| |
Compare Logical
Characters Long |
CLCL |
0F |
R1,R2 |
| |
Compare Logical
Immediate |
CLI |
95 |
D1(B1),I2 |
| |
Compare Logical
under Mask |
CLM |
BD |
R1,M3,D2(B2) |
| |
Compare Logical
Registers |
CLR |
15 |
R1,R2 |
| |
Compare Packed
(Decimal) |
CP |
F9 |
D1(L1,B1),D2(L2,B2) |
| |
Compare
Registers |
CR |
19 |
R1,R2 |
| |
Compare and
Swap |
CS |
BA |
R1,R3,D2(B2) |
| |
Convert to
Binary |
CVB |
4F |
R1,D2((X2,B2) |
| |
Convert to
Decimal |
CVD |
4E |
R1,D2((X2,B2) |
| |
Divide |
D |
5D |
R1,D2((X2,B2) |
| |
Divide Packed
(Decimal) |
DP |
FD |
D1(L1,B1),D2(L2,B2) |
| |
Divide
Registers |
DR |
1D |
R1,R2 |
| |
Edit |
ED |
DE |
D1(L1,B1),D2(B2) |
| |
Edit and
Mark |
EDMK |
DF |
D1(L1,B1),D2(B2) |
| |
Execute |
EX |
44 |
R1,D2(X2,B2) |
| |
Insert
Character |
IC |
43 |
R1,D2(X2,B2) |
| |
Insert Character
under Mask |
ICM |
BF |
R1,M3,D2(B2) |
| |
Load |
L |
58 |
R1,D2(X2,B2) |
| |
Load
Address |
LA |
41 |
R1,D2(X2,B2) |
| |
Load Complement
Registers |
LCR |
13 |
R1,R2 |
| |
Load
Halfword |
LH |
48 |
R1,D2(X2,B2) |
| |
Load
Multiple |
LM |
98 |
R1,R3,D2(B2) |
| |
Load
Negative |
LNR |
11 |
R1,R2 |
| |
Load
Postive |
LPR |
10 |
R1,R2 |
| |
Load
Register |
LR |
18 |
R1,R2 |
| |
Load and Test
Register |
LTR |
12 |
R1,R2 |
| |
Multipy |
M |
5C |
R1,D2(X2,B2) |
| |
Multipy
Halfword |
MH |
4C |
R1,D2(X2,B2) |
| |
Multipy Packed
(Decimal) |
MP |
FC |
D1(L1,B1),D2(L2,B2) |
| |
Multipy
Registers |
MR |
1C |
R1,R2 |
| |
Move
Characters |
MVC |
D2 |
D1(L,B1),D2(B2) |
| |
Move
Inverse |
MVCIN |
E8 |
D1(L,B1),D2(B2) |
| |
Move Characters
Long |
MVCL |
0E |
R1,R2 |
| |
Move
Immediate |
MVI |
92 |
D1(B1),I2 |
| |
Move
Numerics |
MVN |
D1 |
D1(L,B1),D2(B2) |
| |
Move with
Offset |
MVO |
F1 |
D1(L1,B1),D2(L2,B2) |
| |
Move Zones |
MVZ |
D3 |
D1(L,B1),D2(B2) |
| |
aNd |
N |
54 |
R1,D2(X2,B2) |
| |
aNd
Characters |
NC |
D4 |
D1(L,B1),D2(B2) |
| |
aNd
Immediate |
NI |
94 |
D1(B1),I2 |
| |
aNd
Registers |
NR |
14 |
R1,R2 |
| |
Or |
O |
56 |
R1,D2(X2,B2) |
| |
Or
Characters |
OC |
D6 |
D1(L,B1),D2(B2) |
| |
Or
Immediate |
OI |
96 |
D1(B1),I2 |
| |
Or
Registers |
OR |
16 |
R1,R2 |
| |
Pack |
PACK |
F2 |
D1(L1,B1),D2(L2,B2) |
| |
Subtract |
S |
5B |
R1,D2(X2,B2) |
| |
Subtract
Halfword |
SH |
4B |
R1,D2(X2,B2) |
| |
Subtract
Logical |
SL |
5F |
R1,D2(X2,B2) |
| |
Shift Left
Single |
SLA |
8B |
R1,D2(B2) |
| |
Shift Left
Double |
SLDA |
8F |
R1,D2(B2) |
| |
Shift Left Double
Logical |
SLDL |
8D |
R1,D2(B2) |
| |
Shift Left Single
Logical |
SLL |
89 |
R1,D2(B2) |
| |
Subtract Logical
Registers |
SLR |
1F |
R1,R2 |
| |
Subtract Packed
(Decimal) |
SP |
FB |
D1(L1,B1),D2(L2,B2) |
| |
Subtract
Registers |
SR |
1B |
R1,R2 |
| |
Shift Right
Single |
SRA |
8A |
R1,D2(B2) |
| |
Shift Right
Double |
SRDA |
8E |
R1,D2(B2) |
| |
Shift Right Double
Logical |
SRDL |
8C |
R1,D2(B2) |
| |
Shift Right Single
Logical |
SRL |
88 |
R1,D2(B2) |
| |
Shift and Round
Decimal |
SRP |
F0 |
D1(L1,B1),D2(B2),I3 |
| |
Store |
ST |
50 |
R1,D2(X2,B2) |
| |
Store
Character |
STC |
42 |
R1,D2(X2,B2) |
| |
Store Character
under Mask |
STCM |
BE |
R1,M3,D2(B2) |
| |
Store
Halfword |
STH |
40 |
R1,D2(X2,B2) |
| |
Store
Multiple |
STM |
90 |
R1,R3,D2(B2) |
| |
Supervisor
Call |
SVC |
0A |
I1 |
| |
Test under
Mask |
TM |
91 |
D1(B1),I2 |
| |
Translate |
TR |
DC |
D1(L1,B1),D2(B2) |
| |
Translate and
Test |
TRT |
DD |
D1(L1,B1),D2(B2) |
| |
Unpack |
UNPK |
F3 |
D1(L1,B1),D2(L2,B2) |
| |
eXclusive
Or |
X |
57 |
R1,D2(X2,B2) |
| |
eXclusive Or
Characters |
XC |
D7 |
D1(L,B1),D2(B2) |
| |
eXclusive Or
Immediate |
XI |
97 |
D1(B1),I2 |
| |
eXclusive Or
Registers |
XR |
17 |
R1,R2 |
| |
Zero Add
Packed |
ZAP |
F8 |
D1(L1,B1),D2(L2,B2) |
The following list is sequenced by the Hexadecimal Opcode.
| |
Instruction |
Mnemonic |
Hex |
Format |
| |
Branch and Link
Register |
BALR |
05 |
R1,R2 |
| |
Branch on Count
Register |
BCTR |
06 |
R1,R2 |
| |
Branch on Condition
Register |
BCR |
07 |
M1,R2 |
| |
Supervisor
Call |
SVC |
0A |
I1 |
| |
Branch and Set
Mode |
BSM |
0B |
R1,R2 |
| |
Branch, Save and
Set Mode |
BASSM |
0C |
R1,R2 |
| |
Branch and Save
Register |
BASM |
0D |
R1,R2 |
| |
Move Characters
Long |
MVCL |
0E |
R1,R2 |
| |
Compare Logical
Characters Long |
CLCL |
0F |
R1,R2 |
| |
Load
Postive |
LPR |
10 |
R1,R2 |
| |
Load
Negative |
LNR |
11 |
R1,R2 |
| |
Load and Test
Register |
LTR |
12 |
R1,R2 |
| |
Load Complement
Registers |
LCR |
13 |
R1,R2 |
| |
aNd
Registers |
NR |
14 |
R1,R2 |
| |
Compare Logical
Registers |
CLR |
15 |
R1,R2 |
| |
Or
Registers |
OR |
16 |
R1,R2 |
| |
eXclusive Or
Registers |
XR |
17 |
R1,R2 |
| |
Load
Register |
LR |
18 |
R1,R2 |
| |
Compare
Registers |
CR |
19 |
R1,R2 |
| |
Add
Registers |
AR |
1A |
R1,R2 |
| |
Subtract
Registers |
SR |
1B |
R1,R2 |
| |
Multipy
Registers |
MR |
1C |
R1,R2 |
| |
Divide
Registers |
DR
|
1D |
R1,R2 |
| |
Add Logical
Registers |
ALR |
1E |
R1,R2 |
| |
Subtract Logical
Registers |
SLR |
1F |
R1,R2 |
| |
Store
Halfword |
STH |
40 |
R1,D2(X2,B2) |
| |
Load
Address |
LA |
41 |
R1,D2(X2,B2) |
| |
Store
Character |
STC |
42 |
R1,D2(X2,B2) |
| |
Insert
Character |
IC |
43 |
R1,D2(X2,B2) |
| |
Execute |
EX |
44 |
R1,D2(X2,B2) |
| |
Branch and
Link |
BAL |
45 |
R1,D2(X2,B2) |
| |
Branch on
Count |
BCT |
46 |
R1,D2((X2,B2) |
| |
Branch on
Condition |
BC |
47 |
M1,D2(X2,B2) |
| |
Load
Halfword |
LH |
48 |
R1,D2(X2,B2) |
| |
Compare
Halfword |
CH |
49 |
R1,D2(X2,B2) |
| |
Add
Halfword |
AH |
4A |
R1,D2(X2,B2) |
| |
Subtract
Halfword |
SH |
4B |
R1,D2(X2,B2) |
| |
Multipy
Halfword |
MH |
4C |
R1,D2(X2,B2) |
| |
Branch and
Save |
BAS |
4D |
R1,D2(X2,B2) |
| |
Convert to
Decimal |
CVD |
4E |
R1,D2((X2,B2) |
| |
Convert to
Binary |
CVB |
4F |
R1,D2((X2,B2) |
| |
Store |
STb |
50 |
R1,D2(X2,B2) |
| |
aNd |
N |
54 |
R1,D2(X2,B2) |
| |
Compare
Logical |
CL |
55 |
R1,D2(X2,B2) |
| |
Or |
O |
56 |
R1,D2(X2,B2) |
| |
eXclusive
Or |
X |
57 |
R1,D2(X2,B2) |
| |
Load |
L |
58 |
R1,D2(X2,B2) |
| |
Compare |
C |
59 |
R1,D2(X2,B2) |
| |
Add |
A |
5A |
R1,D2(X2,B2) |
| |
Subtract |
S |
5B |
R1,D2(X2,B2) |
| |
Multipy |
M |
5C |
R1,D2(X2,B2) |
| |
Divide |
D |
5D |
R1,D2((X2,B2) |
| |
Add
Logical |
AL |
5E |
R1,D2(X2,B2) |
| |
Subtract
Logical |
SL |
5F |
R1,D2(X2,B2) |
| |
Branch on Index
High |
BXH |
86 |
R1,R3,D2(B2) |
| |
Branch on Index
Low/Equal |
BXLE |
87 |
R1,R3,D2(B2) |
| |
Shift Right Single
Logical |
SRL |
88 |
R1,D2(B2) |
| |
Shift Left Single
Logical |
SLL |
89 |
R1,D2(B2) |
| |
Shift Right
Single |
SRA |
8A |
R1,D2(B2) |
| |
Shift Left
Single |
SLA |
8B |
R1,D2(B2) |
| |
Shift Right Double
Logical |
SRDL |
8C |
R1,D2(B2) |
| |
Shift Left Double
Logical |
SLDL |
8D |
R1,D2(B2) |
| |
Shift Right
Double |
SRDA |
8E |
R1,D2(B2) |
| |
Shift Left
Double |
SLDA |
8F |
R1,D2(B2) |
| |
Store
Multiple |
STM |
90 |
R1,R3,D2(B2) |
| |
Test under
Mask |
TM |
91 |
D1(B1),I2 |
| |
Move
Immediate |
MVI |
92 |
D1(B1),I2 |
| |
aNd
Immediate |
NI |
94 |
D1(B1),I2 |
| |
Compare Logical
Immediate |
CLI |
95 |
D1(B1),I2 |
| |
Or
Immediate |
OI |
96 |
D1(B1),I2 |
| |
eXclusive Or
Immediate |
XI |
97 |
D1(B1),I2 |
| |
Load
Multiple |
LM |
98 |
R1,R3,D2(B2) |
| |
Compare and
Swap |
CS |
BA |
R1,R3,D2(B2) |
| |
Compare Double and
Swap |
CDS |
BB |
R1,R3,D29B2) |
| |
Compare Logical
under Mask |
CLM |
BD |
R1,M3,D2(B2) |
| |
Store Character
under Mask |
STCM |
BE |
R1,M3,D2(B2) |
| |
Insert Character
under Mask |
ICM |
BF |
R1,M3,D2(B2) |
| |
Move
Numerics |
MVN |
D1 |
D1(L,B1),D2(B2) |
| |
Move
Characters |
MVC |
D2 |
D1(L,B1),D2(B2) |
| |
Move Zones |
MVZ |
D3 |
D1(L,B1),D2(B2) |
| |
aNd
Characters |
NC |
D4 |
D1(L,B1),D2(B2) |
| |
Compare Logical
Characters |
CLC |
D5 |
D1(L,B1),D2(B2) |
| |
Or
Characters |
OC |
D6 |
D1(L,B1),D2(B2) |
| |
eXclusive Or
Characters |
XC |
D7 |
D1(L,B1),D2(B2) |
| |
Translate |
TR |
DC |
D1(L1,B1),D2(B2) |
| |
Translate and
Test |
TRT |
DD |
D1(L1,B1),D2(B2) |
| |
Edit |
ED |
DE |
D1(L1,B1),D2(B2) |
| |
Edit and
Mark |
EDMK |
DF |
D1(L1,B1),D2(B2) |
| |
Move
Inverse |
MVCIN |
E8 |
D1(L,B1),D2(B2) |
| |
Shift and Round
Decimal |
SRP |
F0 |
D1(L1,B1),D2(B2),I3 |
| |
Move with
Offset |
MVO |
F1 |
D1(L1,B1),D2(L2,B2) |
| |
Pack |
PACK |
F2 |
D1(L1,B1),D2(L2,B2) |
| |
Unpack |
UNPK |
F3 |
D1(L1,B1),D2(L2,B2) |
| |
Zero Add
Packed |
ZAP |
F8 |
D1(L1,B1),D2(L2,B2) |
| |
Compare Packed
(Decimal) |
CP |
F9 |
D1(L1,B1),D2(L2,B2) |
| |
Add Packed
(Decimal) |
AP |
FA |
D1(L1,B1),D2(L2,B2) |
| |
Subtract Packed
(Decimal) |
SP |
FB |
D1(L1,B1),D2(L2,B2) |
| |
Multipy Packed
(Decimal) |
MP |
FC |
D1(L1,B1),D2(L2,B2) |
| |
Divide Packed
(Decimal) |
DP |
FD |
D1(L1,B1),D2(L2,B2) |
This program may serve as a tutorial for programmers that are new to 370
assembler or as a reference for experienced programmers.
The full word (4 bytes) located at the storage address specified by
operand-2 (x2+b2+d2} is added to the register specified by operand-1(r1).
Operand-2 remains unchanged. The condition code is set as shown below.
| |
|
|
x2=index b2=base register ddd2=displacement |
|
|
| |
|
|
|
|
| |
|
|
|
Condition Code
| 0 |
- |
op1=0, n/o |
| 1 |
- |
op1<0, n/o |
| 2 |
- |
op1>0, n/o |
| 3 |
- |
overflow |
|
| |
|
R1,D2(X2,B2) |
|
|
The half word (2 bytes) located at the storage address specified by
operand-2 (x2+b2+d2) is added to the register specified by operand-1 (r1).
Operand-2 remains unchanged. The condition code is set as shown below.
| |
|
|
x2=index b2=base register ddd2=displacement |
|
|
| |
|
|
|
|
| |
|
|
|
Condition Code
| 0 |
- |
op1=0, n/o |
| 1 |
- |
op1<0, n/o |
| 2 |
- |
op1>0, n/o |
| 3 |
- |
overflow |
|
| |
|
R1,D2(X2,B2) |
|
|
The full word (4 bytes) located at the storage address specified by
operand-2 (x2+b2+d2) is added to the register specified by operand-1 (r1).
Operand-2 remains unchanged. The condition code is set as shown below.
| |
|
|
x2=index b2=base register ddd2=displacement |
|
|
| |
|
|
|
|
| |
|
|
|
Condition Code
| 0 |
- |
zero, no-carry |
| 1 |
- |
not-zero, no-carry |
| 2 |
- |
zero, carry |
| 3 |
- |
not-zero, carry |
|
| |
|
R1,D2(X2,B2) |
|
|
The register specified by operand-2 (r2) is added to the register
specified by operand-1 (r1). Operand-2 remains unchanged. The condition code is
set as shown below.
| |
|
|
|
|
| |
|
|
|
Condition Code
| 0 |
- |
zero, no-carry |
| 1 |
- |
not-zero, no-carry |
| 2 |
- |
zero, carry |
| 3 |
- |
not-zero, carry |
|
| |
|
R1,R2 |
|
|
The data string located at the storage address specified by operand-2
(b2+d2) is added to the data string located at the storage address specified by
operand-1 (b1+d1). Operand-2 remains unchanged. The operands may be different
lengths with a maximum length of 16 bytes (or 31 digits since this is packed)
for each operand. The condition code is set as shown below.
| |
|
|
b2=base register ddd2=displacement |
|
|
| |
|
|